RFID Systems with Low Complexity Implementation and Pallet Coding Error Correction

• US 20150371067A1
• Filed: 02/19/2015
• Published: 12/24/2015
• Est. Priority Date: 10/28/2005
• Status: Abandoned Application

• Current Assignee: Mojix Inc
• Original Assignee: Mojix Inc
• Inventors: Sadr, Ramin
• Application Number:
  US14/626,874
• Publication Number:
  US 20150371067A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06K 7/10019 resolving collision on the communication channels between simultaneously or concurrently interrogated record carriers. collision between the communication channels used by wireless communication devices, where the solution is not particularly adapted for RFIDs or the like, H04W74/08
• CPC Class Codes: G06K 7/10366 the interrogation device being adapted for miscellaneous applications
• CPC Class Codes: H03M 13/098 using single parity bit
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/3905 Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
• CPC Class Codes: H03M 13/6331 Error control coding in combination with equalisation
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 27/0014 Carrier regulation of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657

Abstract

Systems and methods for decoding data transmitted by RFID tags are disclosed. One embodiment of the invention includes an analyzer and equalizer configured to filter an input signal, an estimation block configured to obtain a baseband representation of the modulated data signal by mixing the filtered input signal with the carrier wave, and a coherent detector configured to perform phase and timing recovery on the modulated data signal in the presence of noise and to determine a sequence of data symbols.

Claims

1. A receiver configured to decode a data signal modulated onto a carrier wave, where the phase and timing of the data signal is ambiguous, comprising:

an analyzer and equalizer configured to filter an input signal;

an estimation block configured to obtain a baseband representation of the modulated data signal by mixing the filtered input signal with the carrier wave; and

a coherent detector configured to perform phase and timing recovery on the modulated data signal in the presence of noise and to determine a sequence of data symbols.

2. The receiver of claim 1, wherein the analyzer and equalizer is configured to filter at least one source of narrowband interference from the input signal.

3. The receiver of claim 2, wherein the analyzer and equalizer includes a low latency notch filter, where the location of the notch can be moved to eliminate sources of narrowband interference from the input signal.

4. The receiver of claim 3, wherein:

the notch filter is implemented using a filter bank with an impulse response determined by a set of filter bank coefficients; and

the analyzer and equalizer estimates the channel impulse response and uses it to determine the filter bank coefficients.

5. The receiver of claim 3, wherein the notch filter is configured to adapt the location of the notch based upon an output of the detector.

6. The receiver of claim 1, wherein the estimation block receives the carrier wave as an input.

7. The receiver of claim 1, wherein the estimation block is configured to estimate the frequency of the carrier wave.

8. The receiver of claim 7, wherein:

the estimation block is configured to control a programmable oscillator; and

the estimation block is configured to estimate the frequency difference between the transmitted carrier wave and the output of the programmable oscillator and to reconfigure the programmable oscillator to reduce the frequency difference.

9. The receiver of claim 1, wherein the coherent detector includes a coherent decoder that determines the sequence of symbols with the maximum a posteriori probability of having been transmitted given the data signal.

10. The receiver of claim 9, wherein the coherent decoder is configured using a finite state machine to model the observation space.

11. The receiver of claim 10, wherein the finite state machine incorporates symbol phase estimation.

12. The receiver of claim 10, wherein the finite state machine incorporates symbol timing estimation.

13. The receiver of claim 9, wherein:

the data signal is channel coded;

the coherent decoder comprises;

a soft metric estimator;

a de-interleaver;

a soft input soft output (SISO) decoder;

an interleaver; and

a channel code decoder;

the soft metric estimator is configured to calculate initial soft metrics using the data signal and a fixed phase value, timing value and channel state estimated by the channel code decoder during a previous iteration;

the de-interleaver is configured to de-interleave an input generated by subtracting the output generated by the interleaver in a previous iteration from the initial soft metrics;

the SISO decoder is configured to generate updated soft metrics using the output of the de-interleaver;

the interleaver is configured to interleave an input generated by subtracting the output of the de-interleaver from the updated soft metrics;

the channel code decoder is configured to estimate a phase value, a timing value and channel state from the output of the interleaver; and

the coherent decoder is configured to iterate until the initial soft metrics and the updated soft metrics converge.

14. The receiver of claim 13, wherein:

the coherent decoder determines the maximum soft metric and outputs the maximum soft metric; and

coherent decoder uses predetermined probabilities to augment at least some of the maximum soft metrics.

15. The receiver of claim 13, wherein the channel code decoder includes a soft input soft output forward error correction decoder.

16. The receiver of claim 1, wherein:

the sequence of symbols includes a preamble known by the receiver;

the coherent detector includes an interpolator that is configured to sample and interpolate the data signal to generate a plurality of streams possessing different symbol rates;

the coherent detector includes a correlator that is configured to select a stream using at least the correlation between the stream and the known preamble; and

the coherent detector is configured to provide the selected stream to a decoder.

17. The receiver of claim 16, wherein:

at least a portion of the sequence of symbols is constrained to a predetermined set of allowed symbol transitions; and

the correlator is configured to select a stream using at least the correlation between the stream and the known preamble and the correlation between the stream symbol transitions and the allowed symbol transitions.

18. A system for interrogating radio frequency identification (RFID) tags, comprising:

an exciter in a first location configured to activate an RFID tag; and

a receiver in a second location for receiving information from an activated RFID tag;

wherein the exciter and the receiver are configured to communicate via at least one wireless link; and

wherein the receiver is configured to provide information to transmit to an activated RFID tag that is responsive to information decoded from signals received from the activated RFID tag to the exciter via the wireless link.

19. The system of claim 18, wherein the receiver is configured to perform phase and timing recovery on a signal received from an activated RFID tag.

20. The system of claim 18, wherein the receiver is configured to decode information received from an activated RFID tag by determining the sequence of symbols with the maximum a posteriori probability of having been transmitted based upon the signal received from the activated RFID tag.