DISPLAY PANEL, PIXEL CHIP, AND ELECTRONIC APPARATUS

• US 20150371591A1
• Filed: 12/20/2013
• Published: 12/24/2015
• Est. Priority Date: 01/11/2013
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: SUZUKI, Hideyuki, MIYAUCHI, Toshiyuki, MIYAJIMA, Yoshifumi, HATTORI, Masayuki, TAKANOHASHI, Kazukuni, TOGASHI, Haruo, IKEDA, Tamotsu, OOTORII, Hiizu, UENO, Yosuke, TANAKA, Sachiya
• Granted Patent: US 9,905,151 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2230/00 Details of flat display driving waveforms
• CPC Class Codes: G09G 2310/02 Addressing, scanning or driving the display screen or processing steps related thereto
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3291 in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: G09G 3/36 using liquid crystals

Abstract

A display panel includes a plurality of first unit pixels (Pix) each including: a first data input terminals (PDIN); a first data output terminal (PDOUT); a display element (48); and a first waveform shaping section (42, 22), in which the display element (48) is configured to perform display based on first data (PD) inputted to the first data input terminal (PDIN), and the first waveform shaping section (42, 44) is provided on a signal path from the first data input terminal (PDIN) to the first data output terminal (PDOUT).

Claims

1. A display panel, comprising

a plurality of first unit pixels each including:

a first data input terminal;

a first data output terminal;

a display element; and

a first waveform shaping section, the display element being configured to perform display based on first data inputted to the first data input terminal, and the first waveform shaping section being provided on a signal path from the first data input terminal to the first data output terminal.

2. The display panel according to claim 1, further comprising a drive section,

wherein the first data input terminal of one first unit pixel of the plurality of first unit pixels is connected to the first data output terminal of another first unit pixel, and

the drive section is configured to supply the first data to a first-stage first unit pixel of the plurality of the first unit pixels.

3. The display panel according to claim 2,

wherein the plurality of first unit pixels each further include:

a first clock input terminal;

a first clock output terminal; and

a first buffer provided on a first clock signal path from the first clock input terminal to the first clock output terminal.

4. The display panel according to claim 3,

wherein the plurality of first unit pixels each further include:

a second clock input terminal;

a second clock output terminal; and

a second buffer provided on a second clock signal path from the second clock input terminal to the second clock output terminal, and

a first clock and a second clock are inverted in signal level to each other, the first clock being inputted to the first clock input terminal, and the second clock being inputted to the second clock input terminal.

5. The display panel according to claim 2,

wherein the plurality of first unit pixels each further include:

a first clock input terminal;

a second clock input terminal;

a first clock output terminal to be connected to the first clock input terminal in a following-stage first unit pixel;

a second clock output terminal to be connected to the second clock input terminal in the following-stage first unit pixel;

a first inverter provided on a first clock signal path from the first clock input terminal to the second clock output terminal; and

a second inverter provided on a second clock signal path from the second clock input terminal to the first clock output terminal.

6. The display panel according to claim 4,

wherein a latch circuit is interposed between the first clock signal path and the second clock signal path.

7. The display panel according to claim 2,

wherein the plurality of first unit pixels each include:

a second data input terminal;

a second data output terminal; and

a second waveform shaping section provided on a signal path from the second data input terminal to the second data output terminal, and

second data includes a data portion to discriminate, for each first unit pixel, intensity data in the first data, the second data being inputted to the second data input terminal.

8. The display panel according to claim 2, further comprising a second unit pixel connected to the first output terminal in the one first unit pixel of the plurality of first unit pixels.

9. The display panel according to claim 1,

wherein the first data includes intensity data that defines emission intensity in the display element,

the plurality of first unit pixels each further include a memory section that stores the intensity data, and

the display element is configured to perform display with intensity according to the intensity data stored in the memory section.

10. The display panel according to claim 9,

wherein the plurality of first unit pixels each further include a pulse generating section that is configured to generate a pulse signal having a pulse width according to the intensity data stored in the memory section, and

the display element is configured to perform display based on the pulse signal.

11. The display panel according to claim 10,

wherein the pulse generating section is configured with use of a counter.

12. The display panel according to claim 10,

wherein the first waveform shaping section, the memory section, and the pulse generating section constitute a chip for each first unit pixel.

13. The display panel according to claim 9,

wherein the plurality of first unit pixels each further include a converting section that is configured to D/A-convert the intensity data stored in the memory section, and

the display element is configured to perform display based on the D/A-converted intensity data.

14. The display panel according to claim 9,

wherein the first data includes a flag, the first data being inputted to one first unit pixel, and the flag indicating whether the intensity data has been read in a first unit pixel arranged anteriorly to the one first unit pixel of the plurality of first unit pixels, and

the plurality of first unit pixels each are configured to distinguish, based on the flag, intensity data concerning the relevant first unit pixel from the intensity data concerning the plurality of first unit pixels included in the first data.

15. The display panel according to claim 9,

wherein the plurality of first unit pixels are each assigned with an address, and

the plurality of first unit pixels each are configured to distinguish, based on the address, intensity data concerning the relevant first unit pixel from the intensity data concerning the plurality of first unit pixels included in the first data.

16. The display panel according to claim 1,

wherein the first waveform shaping section is a flip-flop.

17. The display panel according to claim 1,

wherein the first waveform shaping section is a buffer.

18. The display panel according to claim 1,

wherein the plurality of first unit pixels each include the display element in a plurality, and

the plurality of display elements are configured to perform display in different colors from one another.

19. The display panel according to claim 1,

wherein the display element is an LED display element.

20. A pixel chip, comprising:

a first data input terminal;

a first data output terminal; and

a first waveform shaping section provided on a signal path from the first data input terminal to the first data output terminal.

21. An electronic apparatus, comprising:

a display panel; and

a control section configured to perform operation control on the display panel,

wherein the display panel includes

a plurality of first unit pixels each including;

a first data input terminal;

a first data output terminal;

a display element; and

a first waveform shaping section, the display element being configured to perform display based on first data inputted to the first data input terminal, and the first waveform shaping section being provided on a signal path from the first data input terminal to the first data output terminal.