THROUGH ARRAY ROUTING FOR NON-VOLATILE MEMORY

• US 20150371925A1
• Filed: 06/20/2014
• Published: 12/24/2015
• Est. Priority Date: 06/20/2014
• Status: Abandoned Application

• Current Assignee: Intel NDTM US LLC (Intel Corporation)
• Original Assignee: Intel Corporation
• Inventors: Thimmegowda, Deepak, Lee, Minsoo, Lindsay, Roger
• Application Number:
  US14/310,391
• Publication Number:
  US 20150371925A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Technologies for routing access lines in non-volatile memory are described. In some embodiments the technologies include forming one or more through array vias in a portion of a memory array in a non-volatile memory, such as in an array region or peripheral region, one or more access lines may be routed through the through array via, instead of within a region above or below an array or peripheral region of the memory array. This can enable alternative routing configurations, and may enable additional access lines to be routed without increasing or substantially increasing the block height of the non-volatile memory. Non-volatile memory employing such technologies is also described.

Claims

1. A non-volatile memory, comprising:

a memory array comprising a stack of alternating dielectric and conductive layers formed on an insulating layer, the memory array further comprising an array region and a peripheral region;

a structure formed under at least one of the array region and peripheral region and electrically coupled to another component of said non-volatile memory; and

a through array via formed in at least one of said array region and said peripheral region;

wherein at least one access line of said memory array is routed through said through array via.

2. The non-volatile memory of claim 1, wherein said through array via is formed in at least said peripheral region.

3. The non-volatile memory of claim 1, wherein said another component comprises driver circuitry for driving at least one memory string of said memory array.

4. The non-volatile memory of claim 3, wherein:

said memory array comprises at least first and second memory arrays each of which comprise a plurality of memory cells; and

said driver circuitry is shared between said first and second memory arrays and is configured to drive the memory cells thereof.

5. The non-volatile memory of claim 4, wherein:

said memory array comprises at least first and second memory arrays each of which comprise a plurality of memory cells; and

said driver circuitry is shared between said first and second memory arrays and is configured to drive the memory cells thereof.

6. The non-volatile memory of claim 1, wherein:

said stack of alternating dielectric and conductive layers has an upper surface;

said through array via comprises at least one high aspect ratio trench that extends from said upper surface to said structure; and

at least one insulating material at least partially fills said trench.

7. The non-volatile memory of claim 6, wherein said at least one insulating material is a combination of borophosphosilicate glass, SiO₂, and a spun on dielectric material.

8. The non-volatile memory of claim 6, wherein:

at least one channel is formed in said insulating material; and

at least one conductive material is formed in said at least one channel.

9. The non-volatile memory of claim 8, wherein said at least one conductive material is in the form of at least one first conductive layer and at least one second conductive layer deposited on the at least one first conductive layer.

10. The non-volatile memory of claim 8, further comprising at least one barrier layer formed between said at least one conductive material and said stack of alternating dielectric and conductive layers.

11. The non-volatile memory of claim 10, wherein said at least one barrier layer is formed from a barrier material selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, tungsten and combinations thereof.

12. The non-volatile memory of claim, 9, further comprising at least one barrier layer formed between said first conductive layer and said stack of alternating dielectric and conductive layers, wherein said at least one barrier layer is formed from a barrier material selected from the group consisting of titanium nitride, tantalum nitride, tungsten nitride, tungsten and combinations thereof.

13. The non-volatile memory of claim 1, wherein said at least one access line comprises at least one of a source line, word line, select gate source line, and a select gate drain line.

14. A method of forming a non-volatile memory, comprising:

providing a memory array comprising a stack of alternating dielectric and conductive layers formed on an insulating layer, the memory array further comprising an array region and a peripheral region;

forming at least one through array via in at least one of said array region and peripheral region, the through array via extending from an upper surface of said stack of alternating dielectric and conductive layers to a structure under at least one of the array region and the peripheral region, the structure being electrically coupled to an another component of said non-volatile memory;

wherein the through array via is configured to enable electrical coupling of at least one access line of said memory array to said structure.

15. The method of claim 14, wherein said memory array comprises a vertical stack of memory cells.

16. The method of claim 14, wherein;

said another component comprises driver circuitry for driving at least one memory string of said memory array;

said memory array comprises at least first and second memory arrays each of which comprise a plurality of memory cells; and

said driver circuitry is shared between said first and second memory arrays and is configured to drive the memory cells thereof.

17. The method of claim 15, wherein:

said stack of alternating dielectric and conductive layers has an upper surface, and said through array extends from said upper surface to said structure; and

forming said at least one through array via comprises forming at least one high aspect ratio trench extending from an upper surface of said alternating dielectric and conductive layers to said structure.

18. The method of claim 17, wherein forming said at least one high aspect ratio trench comprises etching said alternating dielectric and conductive layers with a dry etching process.

19. The method of claim 18, wherein forming said at least one through array via further comprises filling said at least one high aspect ratio trench with at least one insulating material.

20. The method of claim 19, wherein filling said at least one high aspect ratio trench comprises:

depositing borophosphosilicate glass in said at least one high aspect ratio trench;

depositing tetraorthosilicate on said borophosphosilicate glass via chemical vapor deposition;

converting said tetraorthosilicate to silica; and

depositing a spin on dielectric material on at least one of said silica and said borophosphosilicate glass.

21. The method of claim 19, wherein forming said at least one through array via further comprises forming at least one channel in said at least one insulating material that extends from an upper surface of said at least one insulating material to said component.

22. The method of claim 21, wherein forming said at least one through array via further comprises filling said at least on channel with at least one conductive material.

23. The method of claim 22, wherein said at least one conductive material is in the form of at least one first conductive layer and at least one second conductive layer deposited on the at least one first conductive layer.

25. The method of claim 22, further comprising forming at least one barrier layer between said at least one conductive material and said stack of alternating dielectric and conductive layers.

24. The non-volatile of claim 24 wherein said first conductive layer is titanium and the second conductive layer is tungsten.