TRANSISTOR AND SEMICONDUCTOR DEVICE

• US 20150372009A1
• Filed: 06/15/2015
• Published: 12/24/2015
• Est. Priority Date: 06/18/2014
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: YAMAZAKI, Shunpei
• Granted Patent: US 9,887,300 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A transistor with small parasitic capacitance is provided. The transistor includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor includes a first region, a second region, and a third region. The oxide semiconductor includes a fourth region, a fifth region, and a sixth region. The first region has a region where the first region and the sixth region overlap each other with the first insulator positioned therebetween. The second region has a region where the second region and the second conductor overlap each other with the first insulator and the second insulator positioned therebetween. The third region has a region where the third region and the third conductor overlap each other with the first insulator and the second insulator positioned therebetween. The fourth region has a region in contact with the second conductor.

Claims

1. A transistor comprising:

an oxide semiconductor;

a first conductor;

a second conductor;

a third conductor;

a first insulator; and

a second insulator,

wherein the first conductor includes a first region, a second region, and a third region,

wherein the oxide semiconductor includes a fourth region, a fifth region, and a sixth region,

wherein the first region and the sixth region overlap each other with the first insulator positioned between the first region and the sixth region,

wherein the second region and the second conductor overlap each other with the first insulator and the second insulator positioned between the second region and the second conductor,

wherein the third region and the third conductor overlap each other with the first insulator and the second insulator positioned between the third region and the third conductor,

wherein the second conductor is in contact with the fourth region,

wherein the third conductor is in contact with the fifth region, and

wherein the sixth region includes a lower carrier density than the fourth region and the fifth region.

2. A semiconductor device including the transistor according to claim 1, and a p-channel transistor,

wherein the transistor is an n-channel transistor,

wherein a source or a drain of the p-channel transistor is electrically connected to a source or a drain of the n-channel transistor,

wherein a gate of the p-channel transistor is electrically connected to a gate of the n-channel transistor, and

wherein a channel formation region of the p-channel transistor includes silicon.

3. The semiconductor device according to claim 2, wherein the p-channel transistor is formed using a silicon substrate whose crystal plane in a top surface comprises a region of a (110) plane.

4. The semiconductor device according to claim 2, wherein the channel formation region of the p-channel transistor has a concentration gradient where a concentration of an impurity imparting an n-type conductivity gets higher toward a vicinity of a surface of the channel formation region.

5. The semiconductor device according to claim 2, wherein the gate of the p-channel transistor includes a conductor with a work function of 4.5 eV or higher.

6. The semiconductor device according to claim 2, wherein the oxide semiconductor comprises indium.

7. The semiconductor device according to claim 2, wherein the oxide semiconductor includes a first oxide semiconductor, a second oxide semiconductor, and a third oxide semiconductor overlapping each other.

8. A transistor comprising:

an oxide semiconductor;

a first conductor;

a second conductor;

a third conductor;

a first insulator; and

a second insulator,

wherein the first conductor includes a first region, a second region, and a third region,

wherein the oxide semiconductor includes a fourth region, a fifth region, and a sixth region,

wherein the first region and the sixth region overlap each other with the first insulator positioned between the first region and the sixth region,

wherein the second region and the second conductor overlap each other with the first insulator and the second insulator positioned between the second region and the second conductor,

wherein the third region and the third conductor overlap each other with the first insulator and the second insulator positioned between the third region and the third conductor,

wherein the second conductor is in contact with the fourth region,

wherein the third conductor is in contact with the fifth region, and

wherein the sixth region includes a lower conductivity than the fourth region and the fifth region.

9. A semiconductor device including the transistor according to claim 8, and a p-channel transistor,

wherein the transistor is an n-channel transistor,

wherein a source or a drain of the p-channel transistor is electrically connected to a source or a drain of the n-channel transistor,

wherein a gate of the p-channel transistor is electrically connected to a gate of the n-channel transistor, and

wherein a channel formation region of the p-channel transistor includes silicon.

10. The semiconductor device according to claim 9, wherein the p-channel transistor is formed using a silicon substrate whose crystal plane in a top surface comprises a region of a (110) plane.

11. The semiconductor device according to claim 9, wherein the channel formation region of the p-channel transistor has a concentration gradient where a concentration of an impurity imparting an n-type conductivity gets higher toward a vicinity of a surface of the channel formation region.

12. The semiconductor device according to claim 9, wherein the gate of the p-channel transistor includes a conductor with a work function of 4.5 eV or higher.

13. The semiconductor device according to claim 9, wherein the oxide semiconductor comprises indium.

14. The semiconductor device according to claim 9, wherein the oxide semiconductor includes a first oxide semiconductor, a second oxide semiconductor, and a third oxide semiconductor overlapping each other.

15. A transistor comprising:

an oxide semiconductor;

a first conductor;

a second conductor;

a third conductor;

a first insulator; and

a second insulator,

wherein the first conductor includes a first region, a second region, and a third region,

wherein the oxide semiconductor includes a fourth region, a fifth region, and a sixth region,

wherein the first region and the sixth region overlap each other with the first insulator positioned between the first region and the sixth region,

wherein the second region and the second conductor overlap each other with the first insulator and the second insulator positioned between the second region and the second conductor,

wherein the third region and the third conductor overlap each other with the first insulator and the second insulator positioned between the third region and the third conductor,

wherein the second conductor is in contact with the fourth region,

wherein the third conductor is in contact with the fifth region, and

wherein the sixth region includes a lower hydrogen concentration than the fourth region and the fifth region.

16. A semiconductor device including the transistor according to claim 15, and a p-channel transistor,

wherein the transistor is an n-channel transistor,

wherein a source or a drain of the p-channel transistor is electrically connected to a source or a drain of the n-channel transistor,

wherein a gate of the p-channel transistor is electrically connected to a gate of the n-channel transistor, and

wherein a channel formation region of the p-channel transistor includes silicon.

17. The semiconductor device according to claim 16, wherein the p-channel transistor is formed using a silicon substrate whose crystal plane in a top surface comprises a region of a (110) plane.

18. The semiconductor device according to claim 16, wherein the channel formation region of the p-channel transistor has a concentration gradient where a concentration of an impurity imparting an n-type conductivity gets higher toward a vicinity of a surface of the channel formation region.

19. The semiconductor device according to claim 16, wherein the gate of the p-channel transistor includes a conductor with a work function of 4.5 eV or higher.

20. The semiconductor device according to claim 16, wherein the oxide semiconductor comprises indium.

21. The semiconductor device according to claim 16, wherein the oxide semiconductor includes a first oxide semiconductor, a second oxide semiconductor, and a third oxide semiconductor overlapping each other.