ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

• US 20150372024A1
• Filed: 11/20/2014
• Published: 12/24/2015
• Est. Priority Date: 06/19/2014
• Status: Active Grant

• Current Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: WANG, Xiao
• Granted Patent: US 9,331,105 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3205 Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers manufacture of electrodes H01L21/28
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/78636 with supplementary region or layer for improving the flatness of the device

Abstract

The invention discloses an array substrate, a manufacturing method thereof and a display device. The array substrate includes a gate, an active layer, a source and a drain on a substrate, and a pixel electrode located above the drain and lapped with the drain, and a part of the pixel electrode lapped with the drain is a lapping part of the pixel electrode; the array substrate further includes a first insulation layer located below the pixel electrode and in contact with the drain, the first insulation layer extends along the edge of the lapping part towards a direction away from the lapping part, part of the drain to be in contact with the lapping part is exposed from the first insulation layer, and the plane where the upper surface of the first insulation layer is located is lower than the plane where the upper surface of the drain is located.

Claims

1. An array substrate, comprising:

a gate, a gate insulation layer, an active layer, a source and a drain, which are disposed on a substrate; and

a pixel electrode located above the drain and lapped with the drain, and a part of the pixel electrode lapped with the drain is a lapping part of the pixel electrode, wherein the array substrate further comprises;

a first insulation layer located below the pixel electrode and in contact with the drain, wherein the first insulation layer extends along the edge of the lapping part towards a direction away from the lapping part, a part of the drain in contact with the lapping part is exposed from the first insulation layer, and the plane where the upper surface of the first insulation layer is located is lower than the plane where the upper surface of the drain is located.

2. The array substrate of claim 1, wherein the first insulation layer is provided with an opening corresponding to a region other than the lapping part of the pixel electrode.

3. The array substrate of claim 1, wherein the first insulation layer extends along the edge of the lapping part towards the direction away from the lapping part to cover the active layer exposed between the source and the drain.

4. The array substrate of claim 1, wherein the source, the drain and the active layer are arranged in the same layer;

and the thickness of the first insulation layer is smaller than that of the drain.

5. The array substrate of claim 1, wherein the source and the drain are located above the active layer, and form a laminated structure together with the active layer;

and

the thickness of the first insulation layer is smaller than the sum of the thicknesses of the drain and the active layer.

6. The array substrate of claim 1, wherein the first insulation layer is a silicon nitride film layer or a silicon oxide film layer.

10. A display device, comprising the array substrate of claim 1.

7. A manufacturing method of an array substrate, comprising:

a step of forming a gate, a gate insulation layer, an active layer, a source and a drain on a substrate, and a step of forming a first insulation layer and a pixel electrode, wherein the pixel electrode is lapped with the drain, and a part of the pixel electrode lapped with the drain is a lapping part of the pixel electrode;

wherein the step of forming the first insulation layer and the pixel electrode comprises;

forming the first insulation layer and the pixel electrode on the substrate formed with the gate, the gate insulation layer, the active layer, the source and the drain, wherein the first insulation layer is located between the pixel electrode and the gate insulation layer and extends along the edge of the lapping part towards the direction away from the lapping part, a part of the drain in contact with the lapping part is exposed from the first insulation layer, and the plane where the upper surface of the first insulation layer is located is lower than the plane where the upper surface of the drain is located;

the pixel electrode is arranged on the drain and the first insulation layer and is lapped with the exposed part of the drain.

8. The manufacturing method of an array substrate of claim 7, wherein the step of forming the gate, the gate insulation layer, the active layer, the source and the drain on the substrate comprises:

forming a pattern including the gate on the substrate;

forming the gate insulation layer on the substrate on which the gate is formed; and

forming a pattern including the active layer, the source and the drain on the substrate formed with the gate insulation layer.

9. The manufacturing method of an array substrate of claim 8, wherein the step of forming a pattern including the active layer, the source and the drain on the substrate on which the gate insulation layer is formed comprises:

forming a semiconductor thin film on the substrate on which the gate insulation layer is formed;

forming a conductive film layer on the semiconductor thin film; and

patterning the conductive film layer and the semiconductor thin film through a single patterning process, in order to form a pattern of the mutually insulated source and the drain, and a pattern of the active layer located below the source and the drain;

or

forming a semiconductor thin film on the substrate on which the gate insulation layer is formed, and patterning the semiconductor thin film through a patterning process to form a pattern of the active layer;

forming a conductive film layer on the substrate on which the pattern of the active layer is formed, and performing a patterning process on the conductive film layer so as to form a pattern of the source and the drain.