Semiconductor Switching Device with Different Local Threshold Voltage

• US 20150372086A1
• Filed: 06/20/2014
• Published: 12/24/2015
• Est. Priority Date: 06/20/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Fachmann, Christian, Vecino Vazquez, Enrique
• Granted Patent: US 9,349,795 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/22 Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0635 in combination with bipolar transistors and diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a semiconductor substrate having a plurality of switchable cells defining an active area of the semiconductor device, an outer rim, and an edge termination region arranged between the switchable cells and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. A source metallization is in ohmic contact with the source regions of the switchable cells. A a gate metallization is in ohmic contact with the gate electrode structures of the switchable cells. The active area defined by the switchable cells includes at least a first switchable region having a first threshold and at least a second switchable region having a second threshold which is higher than the first threshold. An area assumed by the first switchable region is larger than an area assumed by the second switchable region.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising a plurality of switchable cells defining an active area of the semiconductor device, an outer rim, and an edge termination region arranged between the switchable cells and the outer rim, each of the switchable cells comprising a body region, a gate electrode structure and a source region;

a source metallization in ohmic contact with the source regions of the switchable cells; and

a gate metallization in ohmic contact with the gate electrode structures of the switchable cells;

wherein the active area defined by the switchable cells comprises at least a first switchable region having a first threshold and at least a second switchable region having a second threshold which is higher than the first threshold, and

wherein an area assumed by the first switchable region is larger than an area assumed by the second switchable region.

2. The semiconductor device of claim 1, wherein the second switchable region is arranged between the gate metallization and the first switchable region.

3. The semiconductor device of claim 2, wherein the threshold voltage of the first and second switchable region continuously decreases with increasing distance from the gate metallization.

4. The semiconductor device of claim 2, wherein the threshold voltages of the first and second switchable region decreases step-wise with increasing distance from the gate metallization.

5. The semiconductor device of claim 1, wherein the threshold voltage of the first switchable region is between 3 to 3.5 volt and the threshold voltage of the second switchable region is between 4 to 5.5 volt.

6. The semiconductor device of claim 1, wherein the plurality of switchable cells comprises at least one transistor selected from the group consisting of a MOSFET, a MISFET, an IGBT, a SJFET, and any combinations thereof.

7. The semiconductor device of claim 1, wherein the area assumed by the second switchable region, when seen in a plan view onto the semiconductor substrate, is between 5% and 50% of the total area assumed by the first and second switchable region.

8. The semiconductor device of claim 1, wherein each body region comprises a body contact region having a higher doping concentration than the remaining body region, wherein portions of the body contact regions of the switchable cells arranged in the first switchable region have a doping concentration which is lower than a doping concentration of the body contact regions of the switchable cells arranged in the second switchable region.

9. The semiconductor device of claim 8, wherein the doping concentration of the body contact regions of the first and second switchable region decreases step-wise with increasing distance from the gate metallization.

10. The semiconductor device of claim 8, wherein each body region comprises a body contact region having a higher doping concentration than the remaining body region, wherein portions of the body contact regions of the switchable cells arranged in the second switchable region have an implantation width which is larger than an implantation width of portions of the body contact regions of the switchable cells arranged in the first switchable region.

11. The semiconductor device of claim 10, wherein the width of the implantation of the body contact regions of the first and second switchable regions decreases step-wise with increasing distance from the gate metallization.

12. The semiconductor device of claim 1, wherein each body region comprises a channel region next to the gate electrode structure, wherein portions of the channel regions of the switchable cells arranged in the first switchable region have a doping concentration which is lower than a doping concentration of portions of the channel regions of the switchable cells arranged in the second switchable region.

13. The semiconductor device of claim 12, wherein the doping concentration of the body regions of the first and second switchable regions decreases step-wise with increasing distance from the gate metallization.

14. The semiconductor device of claim 1, wherein the first switchable region forms a central region of the active area, and wherein the first switchable region is at least partially surrounded by the second switchable region.

15. The semiconductor device of claim 1, wherein an outer ring region of the active area comprises switchable cells having a higher threshold voltage than switchable cells located in a central region of the active area, wherein the outer ring region of the active area provides a boundary between the central region of the active area and the edge termination region.

16. A semiconductor device, comprising:

a semiconductor substrate comprising a plurality of switchable cells defining an active area of the semiconductor device, an outer rim, and an edge termination region arranged between switchable cells and the outer rim, each of the switchable cells comprising a body region, a gate electrode structure and a source region, the body region comprising a channel region next to the gate electrode structure;

a source metallization in ohmic contact with the source regions of the switchable cells; and

a gate metallization in ohmic contact with the gate electrode structures of the switchable cells;

wherein the active area defined by the switchable cells comprises at least a first switchable region and a second switchable region different to the first switchable region, wherein portions of the channel regions of the switchable cells arranged in the first switchable region have a doping concentration which is lower than a doping concentration of portions of the channel regions of the switchable cells arranged in the second switchable region.

17. The semiconductor device of claim 16, wherein the second switchable region is arranged between the gate metallization and the first switchable region.

18. The semiconductor device of claim 16, wherein the doping concentration of the body regions of the first and second switchable regions decreases step-wise with increasing distance from the gate metallization.

19. The semiconductor device of claim 16, wherein the doping concentration of the portions of the channel regions of the switchable cells arranged in the second switchable region is between 1.5*10¹⁷/cm³ and 2.5*10¹⁷/cm³, and wherein the doping concentration of the portions of the channel regions of the switchable cells arranged in the first switchable region is between 1*10¹⁷/cm³ and 1.25*10¹⁷/cm³.

20. A method for manufacturing a semiconductor device, comprising:

providing a semiconductor substrate comprising an outer rim, an active area, and an edge termination region arranged between the active area and the outer rim;

forming a plurality of switchable cells in the active area, wherein each of the switchable cells comprises a body region, a gate electrode structure, and a source region, wherein the active area defined by the switchable cells comprises at least a first switchable region having a first threshold and at least a second switchable region having a second threshold which is higher than the first threshold, and wherein an area assumed by the first switchable region is larger than an area assumed by the second switchable region;

forming a source metallization in ohmic contact with the source regions of the switchable cells; and

forming a gate metallization in ohmic contact with the gate electrode structures of the switchable cells.

21. The method of claim 20, wherein each body region comprises a channel region next to the gate electrode structure, the method further comprising:

performing a threshold adjustment implantation process by implanting dopants into the channel regions of the body regions, wherein a first implantation dose is implanted into portions of the channel regions of the switchable cells arranged in the first switchable region and a second implantation dose is implanted into portions of the channel regions of the switchable cells arranged in the second switchable region, wherein the second implantation dose is higher than the first implantation dose.

22. The method of claim 21, wherein performing the threshold adjustment implantation comprises:

forming a body implantation mask and implanting dopants into the channel regions of the body regions of the first and second switchable region by a first implantation process; and

forming an auxiliary implantation mask on the body implantation mask, wherein the auxiliary implantation mask covers the body implantation mask in the first switchable region while leaving regions of the body implantation in the second switchable region uncovered, and implanting dopants into the channel regions of the uncovered body regions in the second switchable region by a second implantation process.

23. The method of claim 22, wherein each body region comprises a body contact region, the method further comprising:

performing a body contact region implantation process by implanting dopants into the body contact regions, wherein a first implantation dose is implanted into portions of the body contact regions of the switchable cells arranged in the first switchable region and a second implantation dose is implanted into portions of the body contact regions of the switchable cells arranged in the second switchable region, wherein the second implantation dose is higher than the first implantation dose.