ASYMMETRIC FORMATION APPROACH FOR A FLOATING GATE OF A SPLIT GATE FLASH MEMORY STRUCTURE

• US 20150372121A1
• Filed: 06/19/2014
• Published: 12/24/2015
• Est. Priority Date: 06/19/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tseng, Yuan-Tai, Wu, Chang-Ming, Liu, Shih-Chang, Chen, Sheng-Chieh
• Granted Patent: US 9,691,883 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

Claims

1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:

a semiconductor substrate including a source region and a drain region;

a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions, wherein the floating gate is arranged between the word line and the erase gate;

a first dielectric sidewall region disposed between the word line and the floating gate; and

a second dielectric sidewall region disposed between the erase and floating gates, wherein a thickness of the first dielectric region is greater than a thickness of the second dielectric sidewall region.

2. The semiconductor structure according to claim 1, wherein the floating gate is asymmetric about an axis running perpendicular to a top surface of the semiconductor substrate.

3. The semiconductor structure according to claim 1, wherein first and second sidewalls of the floating gate are asymmetric about an axis running perpendicular to a top surface of the semiconductor substrate, the first and second sidewalls abutting the first and second dielectric sidewall regions, respectively.

4. The semiconductor structure according to claim 1, wherein the thickness of the first dielectric sidewall region is greater than about 100 Angstroms (A) and the thickness of the second dielectric sidewall region is less than about 20 A.

5. The semiconductor structure according to claim 4, wherein the first dielectric sidewall region is a multilayer oxide-nitride-oxide (ONO) film, and wherein the second dielectric sidewall region is an oxide film sandwiched between the floating gate and the erase gate.

6. The semiconductor structure according to claim 1, further including:

a control gate disposed above the floating gate; and

an inter-gate dielectric region disposed between the control gate and the floating gate.

7. The semiconductor structure according to claim 1, wherein the floating gate includes a ledge adjacent to the erase gate to define a floating gate ledge exhibiting a reduced height relative to a top surface of the floating gate, and wherein the floating gate and control gate have co-planar sidewalls adjacent to the wordline.

8. The semiconductor structure according to claim 7, wherein the second dielectric sidewall region includes a dielectric extension extending to the ledge from a base dielectric region disposed between the semiconductor substrate and the floating gate, the dielectric extension having the thickness of the second dielectric sidewall region.

9. The semiconductor structure according to claim 1, wherein the semiconductor substrate further includes a shared source/drain region, a first individual source/drain region, and a second individual source/drain region, wherein the source and drain regions correspond to the shared source/drain region and the first individual source/drain region, and wherein the semiconductor structure further includes:

a second floating gate, a second word line, and a second erase gate spaced between the shared source/drain region and the second individual source/drain region, wherein the second floating gate is between the second word line and the second erase gate;

a third dielectric sidewall region disposed between the second word line and the second floating gate;

a fourth dielectric sidewall region disposed between the second erase and floating gates, wherein a thickness of the third dielectric sidewall region is greater than a thickness of the fourth dielectric sidewall region.

10. A method of manufacturing a semiconductor structure of a split gate flash memory cell, said method comprising:

receiving a semiconductor substrate that includes a second conductive layer formed over a first conductive layer, wherein the first and second conductive layers are separated from one another by a first dielectric layer;

performing a first etch through both the first dielectric layer and the second conductive layer and partially into the first conductive layer to form a pair of control gates;

performing a second etch to remove peripheral portions of the remaining first conductive layer outside a central region between the control gates, while leaving a portion of the remaining first conductive layer in the central region;

forming a second, conformal dielectric layer over sidewalls of the control gates and over the remaining first conductive layer; and

removing portions of the conformal dielectric layer and the remaining first conductive layer in the central region to form a pair of floating gates arranged under the pair of control gates, respectively.

11. The method according to claim 10, further including:

performing a third etch to remove portions of the conformal dielectric layer that do not line sidewalls of the control gates; and

performing a fourth etch to remove exposed portions of the remaining first conductive layer in the central region and to create the floating gates.

12. The method according to claim 10, further including:

forming a third dielectric layer in the central region to insulate exposed sidewalls of the floating gates;

forming an erase gate in the central region; and

forming word lines adjacent to the control gates and outside the central region.

13. The method according to claim 12, further including:

forming the second, conformal dielectric layer over sidewalls of the control gates and over the remaining first conductive layer with a thickness of greater than about 100 Angstroms (A); and

forming the third dielectric layer in the central region to insulate the exposed sidewalls of the floating gates with a thickness of less than about 20 A.

14. The method according to claim 10, further including:

forming the second, conformal dielectric layer over sidewalls of the control gates and over the remaining first conductive layer using an oxide-nitride-oxide (ONO) film.

15. The method according to claim 10, further including:

masking the central region with a photoresist to create a mask; and

performing the second etch according to the mask to remove the peripheral portions of the remaining first conductive layer outside the central region.

16. The method according to claim 10, further including:

forming the floating gates with a profile asymmetric about an axis running perpendicular to a top surface of the semiconductor substrate.

17. The method according to claim 10, further including:

performing the first etch to form a pair of elevated regions in the remaining first conductive layer above a base region in the remaining first conductive layer, the base region including a uniform thickness;

forming the control gates atop the elevated regions; and

forming the floating gates from the base and elevated regions.

18. The method according to claim 10, further including:

embedding a shared source/drain region and a pair of individual source/drain regions within the semiconductor substrate, each of the shared and individual source/drain regions being one of a source and drain region.

19. The method according to claim 10, further including:

forming first and second sidewalls for each floating gate, the first and second sidewalls asymmetric about an axis running perpendicular to a top surface of the semiconductor substrate.

20. An integrated circuit comprising:

a semiconductor substrate including a shared source/drain region and two individual source/drain regions, the shared and individual source/drain regions spaced along a surface of the semiconductor substrate with the shared source/drain region between the two individual source/drain regions; and

two split gate flash memory cells each corresponding to one of the two individual source/drain regions and comprising;

a floating gate, a word line, and an erase gate spaced over the surface between the shared source/drain region and the corresponding individual source/drain region, wherein the floating gate is arranged between the word line and the erase gate;

a first dielectric sidewall region disposed between the floating gate and the word line; and

a second dielectric sidewall region disposed between the floating and erase gates, wherein the first and second dielectric sidewall regions are asymmetric about an axis perpendicular to the surface.