SEMICONDUCTOR DEVICE INCLUDING OSCILLATOR

• US 20150372685A1
• Filed: 06/19/2015
• Published: 12/24/2015
• Est. Priority Date: 06/24/2014
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: KITAGAWA, KATSUHIRO
• Granted Patent: US 9,559,710 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H03L 7/104 using an additional signal from outside the loop for setting or controlling a parameter in the loop H03L7/107, H03L7/12 take precedence

Abstract

According to the present invention, a ring oscillator coupled to an output node operable to output a clock signal including a first logic level generated by a first odd number of delay circuits, and a second logic level different from the first logic level generated by a second odd number of delay circuits different from the first odd number of delay circuits.

Claims

1. A semiconductor apparatus comprising:

a ring oscillator coupled to an output node configured to output a clock signal including a first logic level generated by a first odd number of delay circuits, and a second logic level different from the first logic level generated by a second odd number of delay circuits different from the first odd number.

2. The semiconductor apparatus as claimed in claim 1, wherein the ring oscillator includes a plurality of unit elements each including a unit delay value.

3. The semiconductor apparatus as claimed in claim 2, wherein the plurality of unit elements includes a plurality of inverters.

4. The semiconductor apparatus as claimed in claim 2, wherein the plurality of unit elements includes a plurality of NAND gates.

5. The semiconductor device as claimed in claim 4, wherein at feast one of the plurality of NAND gates includes an output node coupled to an input node of a NAND gate.

6. A ring oscillator circuit, comprising:

a first NAND gate including a first input node coupled to a first node, a second input node coupled to a second node and an output node coupled to an output terminal;

a second NAND gate including a first input node coupled to a third node, a second input node coupled to the output terminal and an output node coupled to the second node;

a third NAND gate including a first input node operable to couple to a power supply line, a second input node coupled to the first node and an output node coupled to the third node; and

an N number of NAND gates coupled between the first node and the output terminal, wherein N is an even number larger than 1.

7. The circuit as claimed in claim 6, wherein the N number of NAND gates includes a fourth NAND gate including a first input node operable to receive an enable signal.

8. The circuit as claimed in claim 6, wherein the N number of NAND gates includes a fifth NAND gate including a first input node operable to couple to the power supply line.

9. The circuit as claimed in claim 6, wherein the third NAND gate includes an M number of NAND gates coupled between the third node and the output terminal wherein M is odd number larger than 0.

10. The circuit as claimed in claim 6, further comprising a fifth NAND gate including a first input node coupled to the second node and a second input node operable to couple to the power supply line, and a sixth NAND gate including a first input node coupled to the third node and a second input node operable to couple to the power supply line.

11. A delay locked loop (DLL) circuit comprising:

a delay line configured to receive an input clock signal and to delay the input clock signal responsive to a control signal to generate a delayed clock signal;

a phase detector configured to receive the input clock signal and the delayed clock signal and to output a phase difference signal responsive to a phase difference between the input clock signal and the delayed clock signal;

a ring oscillator coupled to an output node and configured to output a clock signal including a first logic level generated by a first odd number of delay circuits, and a second logic level different from the first logic level generated by a second odd number of delay circuits different front the first odd number of delay circuits; and

a control circuit operable to generate the control signal responsive to the clock signal and the phase difference signal.

12. The DLL circuit as claimed in claim 11, wherein the ring oscillator includes a plurality of unit elements each including a unit delay value.

13. The DLL circuit as churned in claim 12, wherein the plurality of unit elements includes a plurality of inverters.

14. The DLL circuit as claimed in claim 12, wherein the plurality of unit elements includes a plurality of NAND gates.

15. The DLL circuit as claimed in claim 14, wherein at least one of the plurality of NAND gates includes an output node coupled to an input node of a NAND gate.

16. The DLL circuit as claimed in claim 11, wherein the control circuit includes:

a counter circuit configured to receive the clock signal and the delayed clock signal and to output a count value responsive to the clock signal and the delayed clock signal;

a divider configured to receive the count value and to output a divided count value; and

an adder configured to receive the divided count value and another control signal and to output the control signal.

17. The DLL circuit as claimed in claim 16, wherein the counter circuit is configured to count a period of the delayed clock signal responsive to the clock signal.