HIGH VOLTAGE MONITORING SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER

• US 20150374997A1
• Filed: 04/22/2015
• Published: 12/31/2015
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Alfred E. Mann Foundation For Scientific Research
• Original Assignee: Alfred E. Mann Foundation For Scientific Research
• Inventors: LEE, EDWARD K. F.
• Granted Patent: US 9,682,237 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: A61N 1/36071 Pain
• CPC Class Codes: A61N 1/36125 Details of circuitry or electric components
• CPC Class Codes: A61N 1/37235 Aspects of the external programmer
• CPC Class Codes: H03M 1/00 Analogue/digital conversion; Digital/analogue conversion conversion of analogue values to or from differential modulation H03M3/00
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/129 Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling H03M1/18 takes precedence; Out-of-range indication
• CPC Class Codes: H03M 1/38 sequentially only, e.g. successive approximation type converting more than one bit per step H03M1/14
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/685 the quantisation value generators of both converters being arranged in a common two-dimensional array
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A successive approximation ADC made of a low voltage configurable differential amplifier and low voltage logic circuits which can convert a high voltage analog input to a digital equivalent. The differential amplifier can be configured as either an op amp or a comparator depending upon the mode of operation. An input capacitor C1 is switchably coupled to an electrode selected for voltage sampling. A switched capacitor array C2 is coupled across the differential amplifier input and output. A SAR coupled to the switched capacitor array provides a digital output corresponding to the sampled analog voltage. During a sampling interval and a charge transfer interval, the differential amplifier is configured as an op amp. During the transfer interval, the voltage on the input capacitor multiplied by the ratio C1/C2 is transferred to the switched capacitor array. During an analog to digital conversion interval, the ADC converts the analog voltage to an equivalent digital output.

Claims

1-30. -30. (canceled)

31. A peripherally-implantable neurostimulation system comprising:

a plurality of leads, wherein each of the plurality of leads comprises at least one electrode; and

an analog-to-digital converter connected to the plurality of leads, wherein the analog-to-digital converter is configurable to operate in a first, sampling mode, and wherein the analog-to-digital converter is reconfigurable to operate in a second, digitization mode.