APPARATUS AND METHOD FOR A USER CONFIGURABLE RELIABILITY CONTROL LOOP

• US 20150377955A1
• Filed: 06/30/2014
• Published: 12/31/2015
• Est. Priority Date: 06/30/2014
• Status: Active Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Shapira, Dorit, Sistla, Krishnakanth V., Rotem, Efraim, Distefano, Eric, Hermerding, James G. II, Natanzon, Esfir
• Granted Patent: US 10,289,514 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/3024 where the computing system component is a central processing unit [CPU]
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.

Claims

1. A processor comprising:

a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions;

a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and

performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.

2. The processor as in claim 1 further comprising:

a reliability management agent (RMA) to provide the stress rate limit information to the controller, the RMA receiving the user input via a user interface.

3. The processor as in claim 2 wherein the RMA provides different rate limits for different time windows specified by the user or manufacturer.

4. The processor as in claim 1 wherein the reliability meter tracks accumulated stress for N characteristics of the processor, wherein N>

1.

5. The processor as in claim 4 wherein the reliability meter outputs N different stress accumulation measurements, one for each of the N characteristics of the processor.

6. The processor as in claim 5 wherein the controller determines N different limits based, at least in part, on operating characteristics of the processor.

7. The processor as in claim 1 wherein the actual operating condition comprises a frequency at which one or more of the portions of the processor operate.

8. The processor as in claim 1 wherein the reliability meter includes a first meter to determine V_ccmin stress and a second meter to determine an accumulated time-dependent dielectric breakdown (TDDB) stress impacting V_max.

9. The processor as in claim 1 wherein the one or more actual operating conditions comprise a plurality of operating conditions specified for a corresponding plurality of domains of the processor.

10. The processor as in claim 9 wherein the processor domains include at least a core domain and a graphics domain.

11. The processor as in claim 1 wherein the reliability meter, controller, and performance selection logic are implemented with a power control unit (PCU) of the processor.

12. A method comprising:

tracking accumulated stress on components of a processor based on measured processor operating conditions;

receiving stress rate limit information from a user or manufacturer and responsively specifying a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and

outputting one or more actual operating conditions for the processor based on the N operating limits specified by the controller.

13. The method as in claim 12 further comprising:

providing different rate limits for different time windows specified by the user or manufacturer.

14. The method as in claim 12 wherein tracking further comprises tracking accumulated stress for N characteristics of the processor, wherein N>

1.

15. The method as in claim 14 further comprising:

outputting N different stress accumulation measurements, one for each of the N characteristics of the processor.

16. The method as in claim 15 further comprising:

determining N different limits based, at least in part, on operating characteristics of the processor.

17. The method as in claim 12 wherein the actual operating condition comprises a frequency at which one or more of the portions of the processor operate.

18. The method as in claim 12 wherein tracking accumulated stress comprises determining V_ccmin stress and determining an accumulated time-dependent dielectric breakdown (TDDB) stress impacting V_max.

19. The method as in claim 12 wherein the one or more actual operating conditions comprise a plurality of operating conditions specified for a corresponding plurality of domains of the processor.

20. The method as in claim 19 wherein the processor domains include at least a core domain and a graphics domain.

21. The method as in claim 12 wherein the operations of tracking, receiving and outputting are implemented with a power control unit (PCU) of the processor.

22. A system comprising:

a memory to store instructions and data;

a cache having a plurality of cache levels to cache the instructions and data;

a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and

a controller to receive stress rate limit information from a user or manufacturer and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and

performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.