SEMICONDUCTOR DEVICE

• US 20150380060A1
• Filed: 10/22/2014
• Published: 12/31/2015
• Est. Priority Date: 06/26/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: HONG, Duck Hwa, PARK, Sang Il
• Granted Patent: US 9,396,773 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 2207/005 Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A semiconductor device includes a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; and second group segment input/output lines disposed to correspond to the second cell to array region when viewed in terms of the dummy bit lines.

Claims

1. A semiconductor device comprising:

a first cell array region disposed adjacent to a second cell array region;

a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines;

first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines;

second group segment input/output lines disposed to correspond to the second cell array region when viewed in terms of the dummy bit lines;

first input/output switching units electrically coupling a first group of the dummy bit lines and bit lines of the first cell array region with the first group segment input/output lines; and

second input/output switching units electrically coupling a second group of the dummy bit lines and bit lines of the second cell array with the second group segment input/output lines,

wherein the first input/output switching units and the second input/output switching units configured to switch in response to a same column select signal.

3. The semiconductor device according to claim 1, wherein the first input/output switching units comprise:

first group dummy switching elements electrically coupled between the dummy bit lines and the first group segment input/output lines and controlled by a column select signal.

4. The semiconductor device according to claim 3, wherein the first input/output switching units further comprise:

a plurality of switching elements electrically coupled with bit lines of the first cell array region and share contacts of segment input/output lines with the first group dummy switching elements.

5. The semiconductor device according to claim 3, wherein the second input/output switching units comprise:

second group dummy switching elements electrically coupled between the dummy bit lines and the second group segment input/output lines and are controlled by the column select signal.

6. The semiconductor device according to claim 5, wherein the second input/output switching units further comprise:

a plurality of switching elements electrically coupled with bit lines of the second cell array region and share contacts of segment input/output lines with the second group dummy switching elements.

7. The semiconductor device according to claim 1, wherein the first input/output switching units and the second input/output switching units are disposed in regions of bit line sense amplifiers.

8. The semiconductor device according to claim 1, further comprising:

switching units configured to selectively control connection between the first group segment input/output lines and the second group segment input/output lines and local input/output lines.

9. The semiconductor device according to claim 1, wherein switching units are disposed in regions of bit line sense amplifiers.

10. The semiconductor device according to claim 1, further comprising:

a segment input/output line precharge unit disposed in an edge region of a bank, and configured to precharge the first group segment input/output lines and the second group segment input/output lines.

11. The semiconductor device according to claim 10, wherein the segment input/output line precharge unit comprises:

a plurality of switching elements which precharge local input/output lines by a precharge signal.

12. The semiconductor device according to claim 11, wherein the segment input/output line precharge unit comprises:

a first switching element electrically coupled between a pair of the local input/output lines, and switched by the precharge signal; and

a second switching element and a third switching element electrically coupled in series between the pair of local input/output lines, and configured to precharge the pair of local input/output lines by the precharge signal.

13. The semiconductor device according to claim 12, wherein the segment input/output line precharge unit precharges the pair of local input/output lines to a level of a core voltage when the precharge signal is activated.

14. The semiconductor device according to claim 10, wherein the segment input/output line precharge unit is disposed under the local input/output lines.

2. (canceled)

15. A semiconductor device comprising:

a plurality of cell array regions including a plurality of memory cells;

a dummy cell region disposed between a first cell array region which is any one of the plurality of cell array regions and a second cell array region disposed adjacent to the first cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines;

first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines;

second group segment input/output lines disposed to correspond to the second cell array region when viewed in terms of the dummy bit lines;

a plurality of bit line sense amplifiers configured to amplify data applied from the plurality of cell array regions and data applied from the dummy bit lines;

first input/output switching units electrically coupling a first group of the dummy bit lines and bit lines of the first cell array region with the first group segment input/output lines; and

second input/output switching units electrically coupling a second group of the dummy bit lines and bit lines of the second cell array with the second group segment input/output lines,

wherein the first input/output switching units and the second input/output switching units configured to switch in response to a same column select signal.

17. The semiconductor device according to claim 15, wherein the first input/output switching units and the second input/output switching units are disposed in regions of the plurality of bit line sense amplifiers.

18. The semiconductor device according to claim 15, further comprising:

switching units configured to selectively control a connection between the first group segment input/output lines and the second group segment input/output lines and local input/output lines.

19. The semiconductor device according to claim 18, wherein the switching units are disposed in regions of the plurality of bit line sense amplifiers.

20. The semiconductor device according to claim 15, further comprising:

a segment input/output line precharge unit disposed in an edge region of a bank, and configured to precharge the first group segment input/output lines and the second group segment input/output lines.

16. (canceled)