STATIC RAM
First Claim
1. A static RAM comprising:
- a plurality of word lines;
a plurality of bit line pairs;
a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines;
a write driver connected between a high potential power source line, whose potential is higher than a reference potential, and a drive line;
a column switch including a first transistor pair which connects one of the plurality of bit line pairs, which is selected, to the write driver; and
a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of write of a memory cell of the plurality of memory cells, whereinthe boost circuit includes;
a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied; and
a boost control transistor connected between the drive line and a reference potential power source line whose potential is the reference potential, and to a gate of the boost control transistor the boost signal is applied, anda threshold value of the boost control transistor is lower than a threshold value of the first transistor pair.
1 Assignment
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Accused Products
Abstract
A static RAM includes: a plurality of memory cells provided at intersections of bit line pairs and word lines; a write driver connected between a high potential power source line and a drive line; a column switch including a first transistor pair which connects one of the plurality of bit line pairs to the write driver; and a boost circuit which boosts the drive line to a negative potential, wherein the boost circuit includes: a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied; and a boost control transistor connected between the drive line and a reference potential power source line, the boost signal is applied to a gate of the boost control transistor, and the threshold value of the boost control transistor is lower than the threshold value of the first transistor pair.
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Citations
6 Claims
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1. A static RAM comprising:
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a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines; a write driver connected between a high potential power source line, whose potential is higher than a reference potential, and a drive line; a column switch including a first transistor pair which connects one of the plurality of bit line pairs, which is selected, to the write driver; and a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of write of a memory cell of the plurality of memory cells, wherein the boost circuit includes; a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied; and a boost control transistor connected between the drive line and a reference potential power source line whose potential is the reference potential, and to a gate of the boost control transistor the boost signal is applied, and a threshold value of the boost control transistor is lower than a threshold value of the first transistor pair. - View Dependent Claims (2)
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3. A static RAM comprising:
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a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines, including a first transistor pair which is selected by the word line and which transfers data with the bit line pair; a write driver connected between a high potential power source line, whose potential is higher than a reference potential, and a drive line; a column switch which selects one of the plurality of bit line pairs and which connects the selected bit line pair to the write driver; and a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of write of a memory cell of the plurality of memory cells, wherein the boost circuit includes; a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied; and a boost control transistor connected between the drive line and a reference potential power source line whose potential is the reference potential, and to a gate of the boost control transistor the boost signal is applied, and a threshold value of the boost control transistor is lower than a threshold value of the first transistor pair.
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4. A static RAM comprising:
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a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines; a write driver connected between a high potential power source line whose potential is higher than a reference potential, and a drive line; a column switch including a first transistor pair which connects one of the plurality of bit line pairs, which is selected, to the write driver; and a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of write of a memory cell of the plurality of memory cells, wherein the boost circuit includes; a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which a boost signal is applied; a boost control transistor connected between the drive line and a reference potential power source line whose potential is the reference potential, and to a gate of the boost control transistor the boost signal is applied; and an over-boost limitation transistor connected between the drive line and the reference potential power source line, and a threshold value of the over-boost limitation transistor is lower than a threshold value of the first transistor pair. - View Dependent Claims (5)
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6. A static RAM comprising:
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a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines, and including a first transistor pair which is selected by the word line and which transfers data with the bit line pair; a write driver connected between a high potential power source line, whose potential is higher than a reference potential, and a drive line; a column switch which selects one of the plurality of bit line pairs and which connects the selected bit line pair to the write driver; and a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at the time of write of a memory cell of the plurality of memory cells, wherein the boost circuit includes; a capacitive element one terminal of which is connected to the drive line, and to the other terminal of which, a boost signal is applied; a boost control transistor connected between the drive line and a reference potential power source line whose potential is the reference potential, and to a gate of the boost control transistor the boost signal is applied; and an over-boost limitation transistor connected between the drive line and the reference potential power source line, and a threshold value of the over-boost limitation transistor is lower than a threshold value of the first transistor pair.
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Specification