MICROELECTRONIC PACKAGES HAVING EMBEDDED SIDEWALL SUBSTRATES AND METHODS FOR THE PRODUCING THEREOF

• US 20150380386A1
• Filed: 06/26/2014
• Published: 12/31/2015
• Est. Priority Date: 06/26/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Michael B. Vincent, Scott M. Hayes
• Inventors: VINCENT, MICHAEL B., HAYES, SCOTT M.
• Granted Patent: US 9,595,485 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0237 Disposition of the redistribution layers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/09 of a plurality of bonding areas
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/35 : Mechanical effects

Abstract

Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method includes producing a molded panel containing a sidewall substrate. The molded panel is singulated to produce a Fan-Out Wafer Level Package core including a molded body having a fan-out region in which the sidewall substrate is embedded. A side connect trace is printed or otherwise formed on a sidewall of the Fan-Out Wafer Level Package core and extends at least partially across the embedded sidewall substrate.

Claims

1. A method for producing a microelectronic package, the method comprising:

embedding a sidewall substrate in a molded panel;

singulating the molded panel to produce a Fan-Out Wafer Level Package (FO-WLP) core having a sidewall at which the sidewall substrate is exposed; and

forming a side connect trace on the sidewall of the FO-WLP core and extending at least partially across the embedded sidewall substrate.

2. The method of claim 1 wherein singulating comprises removing material from the sidewall substrate to impart the sidewall substrate with a singulated surface, and wherein forming comprises forming the sidewall substrate in contact with the singulated surface of the sidewall substrate.

3. The method of claim 2 wherein singulating comprises sawing the molded panel along one or more saw lanes extending through the sidewall substrate.

4. The method of claim 1 further comprising producing the sidewall substrate to include a substrate body composed of a material selected from the group consisting of a resin, a ceramic, silicon, gallium nitride, and gallium arsenide.

5. The method of claim 1 wherein the sidewall substrate comprises a sidewall pad exposed at the sidewall after singulation of the molded panel, and wherein forming comprises forming the side connect trace in contact with the sidewall pad.

6. The method of claim 5 further comprising forming one or more Redistribution Layers (RDLs) over the molded panel prior to singulation thereof, the RDLs containing an interconnect line electrically coupled to the sidewall pad.

7. The method of claim 6 wherein the surface area of the sidewall pad exposed through the sidewall is greater than the cross-sectional area of the interconnect line, as taken along a cut plane orthogonal to an upper principal surface of the RDLs.

8. The method of claim 6 further comprising bonding a second package core to the FO-WLP such that the FO-WLP core and the second package core are disposed in a stacked relationship, the FO-WLP core and the second package core electrically interconnected through the side connect trace.

9. The method of claim 1 further comprising singulating a wafer to produce the sidewall substrate along with a plurality of other sidewall substrates;

and

wherein embedding comprises overmolding the sidewall substrate and the plurality of other sidewall substrates to produce the molded panel.

10. The method of claim 9 further comprising forming at least one metal level over the wafer prior to singulation thereof such that a singulated piece of the wafer defines a body of the sidewall substrate, while a singulated portion the metal level defines an embedded sidewall pad overlying the body of the sidewall substrate.

11. A method for producing a microelectronic package, the method comprising:

producing a first Fan-Out Wafer Level Package (FO-WLP) core including a first molded body, a sidewall substrate embedded in a fan-out region of the first molded body, and a first sidewall pad exposed through the sidewall of the first molded body;

stacking the first FO-WLP core with a second FO-WLP core having a second molded body and a second sidewall pad exposed through the sidewall of the second molded body; and

forming a side connect trace extending from the first sidewall pad, over the sidewall substrate, and to the second sidewall pad to interconnect the first and second FO-WLP cores.

12. The method of claim 11 wherein the first and second FO-WLP cores are stacked while in panel form to yield a panel stack;

wherein the method further comprises singulating the panel stack to define the respective sidewalls of the first and second molded bodies; and

wherein singulating comprises sawing the panel stack along saw lanes, wherein at least one of the saw lanes extends through the sidewall substrate.

13. The method of claim 11 wherein producing comprises producing the first molded body of the FO-WLP core to have a fan-out region in which the sidewall substrate is embedded.

14. A microelectronic package, comprising:

a first Fan-Out Wafer Level Package (FO-WLP) core, comprising;

a molded body having a fan-out region;

a microelectronic component embedded in the molded body adjacent to the fan-out region; and

a sidewall substrate embedded in the fan-out region of the molded body; and

a side connect trace electrically coupled to the microelectronic device and formed at least partially on the embedded sidewall substrate.

15. The microelectronic package of claim 14 wherein the sidewall substrate comprises a sidewall pad, and wherein the side connect trace is electrically coupled to the microelectronic component through the sidewall pad.

16. The microelectronic package of claim 15 further comprising one or more Redistribution Layers (RDLs) formed over the molded body and containing an interconnect line, the interconnect line electrically coupling the microelectronic device to the sidewall pad.

17. The microelectronic package of claim 14 wherein the molded body and the sidewall substrate each comprise a singulated surface, and wherein the singulated surface of the sidewall substrate has a surface roughness less than the singulated surface of the molded body.

18. The microelectronic package of claim 14 further comprising a second package core bonded to the first FO-WLP in a stacked configuration, the first FO-WLP core and the second package core electrically interconnected by the side connect trace.

19. The microelectronic package of claim 18 wherein the first FO-WLP core has a frontside and an opposing backside, wherein the backside of the first FO-WLP core is bonded to the second package core, and wherein the sidewall substrate extends from the frontside to the backside of the first FO-WLP core.

20. The microelectronic package of claim 14 further comprising a second FO-WLP core bonded to the first FO-WLP in a stacked configuration;

wherein the first and second FO-WLP cores comprising first and second sidewall pads, respectively; and

wherein the side connect trace extends from the first sidewall pad to the second sidewall pad to electrically interconnect the first and second FO-WLPs.