METHOD OF SELECTIVELY DEPOSITING FLOATING GATE MATERIAL IN A MEMORY DEVICE

• US 20150380419A1
• Filed: 08/31/2015
• Published: 12/31/2015
• Est. Priority Date: 06/25/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: KINOSHITA, Hiroyuki, MAKALA, Raghuveer S., SHARANGPANI, Rahul, GUNJI-YONEOKA, Marika, SUYAMA, Atusushi, YAMAGUCHI, Kensuke, INOUE, Shigehisa, PHAM, Tuan
• Granted Patent: US 9,768,270 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02087 Cleaning of wafer edges
• CPC Class Codes: H01L 21/0209 Cleaning of wafer backside
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a back side of a substrate, while providing a second material layer only on a front side of the substrate. The first material layer and the second material layer are selected such that a selective deposition process of a metal material provides a metal material portion only on the second material layer, while no deposition occurs on the first material layer or isolated islands of the metal material are formed on the first material layer. Any residual metal material can be removed from the bevel and the back side by a wet etch to reduce or prevent metal contamination from the deposited metal material.

Claims

1. A method of forming a semiconductor structure comprising:

forming a stack comprising a first material layer including a first material and a second material layer including a second material on a front side and a back side of a substrate;

removing the second material layer from a bevel and the back side of the substrate, wherein surfaces of the first material layer are physically exposed at the bevel and the back side;

performing a selective metal deposition process that deposits a metal material at a higher nucleation density on the second material layer than on the first material layer, wherein the metal material is deposited as at least one continuous layer on the second material layer and as isolated islands on the first material layer; and

removing the isolated islands of the metal material from the bevel and the back side while not removing the at least one layer of the metal material.

2. The method of claim 1, wherein removing the isolated islands of the metal material is performed employing a wet etch process that applies a wet etchant chemical to the bevel and to the back side.

3. The method of claim 1, wherein removal of the second material layer from the bevel and the back side of the substrate is performed employing a wet etch process that etches the second material selective to the first material.

4. The method of claim 1, wherein:

the second material is a dielectric material;

the first material is another dielectric material having a greater hydrophobicity than the second material;

the first material has a hydrophobic dielectric surface; and

the second material has a hydrophilic dielectric surface.

5. The method of claim 4, wherein the first material is silicon oxide, and the second material is silicon nitride.

6. The method of claim 4, wherein the metal material is deposited employing an atomic layer deposition process which employs a metal oxide precursor gas, and the metal material is deposited by reduction of adsorbed molecules of the metal oxide precursor gas.

7. The method of claim 6, wherein the atomic layer deposition process employs RuO₄ as a precursor gas, the metal material is ruthenium deposited by reduction of adsorbed molecules of RuO₄.

8. The method of claim 1, wherein the selective metal deposition process is terminated when the isolated islands of the metal material have a maximum dimension not greater than 5 nm.

9. The method of claim 1, further comprising:

applying a photoresist layer over the second material layer;

patterning the photoresist layer to remove portions of the photoresist layer from regions overlying the bevel, wherein a peripheral portion of the second material layer is physically exposed in proximity to the bevel;

removing the physically exposed peripheral portion of the second material layer by an etch process employing the photoresist layer as an etch mask prior to performing the selective metal deposition process; and

removing the patterned photoresist layer.

10. The method of claim 1, further comprising:

forming an intermediate material layer comprising an intermediate material on the first material layer at the front side and the back side of the substrate, wherein the second material layer is formed on the intermediate material layer; and

removing the intermediate material layer from the bevel and the back side of the substrate without removing the intermediate material layer from the front side of the substrate employing another wet etch process.

11. The method of claim 10, wherein:

the metal material comprises ruthenium;

the first material comprises silicon oxide;

the intermediate material comprises a semiconductor material; and

the second material comprises silicon nitride.

12. The method of claim 11, further comprising:

forming at least one trench extending at least through the second material layer and the first material layer; and

filling each of the at least one trench with a respective dielectric material portion prior to performing the selective metal deposition process, wherein the metal material does not cover a predominant portion of each top surface of the at least one dielectric material portion at a time of termination of the selective metal deposition process, and surface of the at least one dielectric material portion is more hydrophobic than a surface of the second material.

13. The method of claim 12, wherein:

the first material comprises a silicon oxide tunnel dielectric;

the intermediate material comprises a polysilicon floating gate;

the second material comprises a silicon nitride charge trapping dielectric;

the metal material comprises a ruthenium capping layer;

the polysilicon floating gate, the silicon nitride charge trapping dielectric and the ruthenium capping layer comprise a hybrid charge storage region of a hybrid NAND memory device;

the dielectric material portion comprises a silicon oxide shallow trench isolation;

the substrate comprises a silicon substrate containing a silicon channel of the hybrid NAND memory device; and

the hybrid NAND memory device further comprises a blocking dielectric and a plurality of control gate electrodes located over the ruthenium capping layer.

14. A hybrid NAND memory device, comprising:

a semiconductor channel located in a substrate;

a shallow trench isolation structure laterally contacting the semiconductor channel;

a tunneling dielectric layer located on the semiconductor channel;

a hybrid floating gate structure comprising a stack of a semiconductor floating gate, a charge trapping dielectric and a metal capping layer located over the tunneling dielectric layer;

a blocking dielectric layer overlying the hybrid floating gate structure; and

a plurality of control gate electrodes overlying the blocking dielectric layer;

wherein the metal capping layer is located entirely above a top surface of the shallow trench isolation structure.

15. The device of claim 14, wherein the blocking dielectric layer is continuous over the shallow trench isolation structure and is located entirely above a top surface of the shallow trench isolation structure.

16. The device of claim 14, wherein:

an interface between the semiconductor floating gate and the charge trapping dielectric is coplanar with the top surface of the shallow trench isolation structure; and

an interface between the blocking dielectric layer and the shallow trench isolation structure is coplanar with the interface between the semiconductor floating gate and the charge trapping dielectric.

17. The device of claim 14, wherein a sidewall of the shallow trench isolation structure contacts sidewalls of the semiconductor channel, the tunneling dielectric layer, the semiconductor floating gate and the charge trapping dielectric, but not the metal capping layer.

18. The device of claim 14, wherein:

the tunneling dielectric layer comprises a silicon oxide layer;

the semiconductor floating gate comprises a polysilicon floating gate;

the charge trapping dielectric comprises a silicon nitride dielectric;

the metal capping layer comprises a ruthenium layer; and

the shallow trench isolation structure comprises silicon oxide.

19. A method of making a NAND memory device comprising a semiconductor channel and a plurality of control gate electrodes, the method comprising selectively forming metal floating gate material on a second dielectric material surface having a lesser hydrophobicity than a first dielectric material surface.

20. The method of claim 19, further comprising:

providing patterned surfaces over a substrate, the patterned surfaces comprising the first dielectric material surface and the second dielectric material surface having the lesser hydrophobicity than the first dielectric material surface; and

performing a selective metal deposition process that deposits the metal floating gate material at a higher nucleation density on the second dielectric material surface than on the first dielectric material surface;

depositing a blocking dielectric and the plurality of control gate electrodes over the metal floating gate material.

21. The method of claim 19, wherein the floating gate metal material is deposited as a metal material portion on the second dielectric material surface and as isolated islands of the metal material on the first dielectric material surface that do does not cover more than 1% the first dielectric material surface.

22. The method of claim 21, wherein:

the isolated islands of the metal material do not physically contact one another, and do not form an electrically conductive path;

the first dielectric material comprises a silicon oxide tunnel dielectric;

the second dielectric material comprises a silicon nitride charge trapping dielectric; and

the metal material comprises ruthenium deposited employing an atomic layer deposition process.

23. The method of claim 22, wherein the atomic layer deposition process employs RuO₄ as a precursor gas, and the is ruthenium deposited by reduction of adsorbed molecules of RuO₄.

24. The method of claim 22, further comprising forming a polysilicon floating gate between the tunnel dielectric and the silicon nitride charge trapping dielectric to form a hybrid charge storage region comprising the polysilicon floating gate, the silicon nitride charge trapping dielectric and the ruthenium capping layer.

25. The method of claim 24, wherein the first dielectric material surface further comprises surfaces of silicon oxide shallow trench isolation regions exposed between stacks comprising the polysilicon floating gate and the silicon nitride charge trapping dielectric.