POWER SEMICONDUCTOR DEVICE
First Claim
1. A power semiconductor device, comprising:
- a first semiconductor layer having a first conductivity type;
a second semiconductor layer having the first conductivity type disposed on the first semiconductor layer, the first semiconductor layer having an effective impurity concentration that is greater than an effective impurity concentration of the second semiconductor layer;
a third semiconductor layer having a second conductivity type that is different from the first conductivity type;
a fourth semiconductor layer comprising a plurality of semiconductor layers having the first conductivity type and the second conductivity type;
a first gate electrode formed between adjacent semiconductor layers of the fourth semiconductor layer, the adjacent layers having the first conductivity type, and the first gate electrode extending to the second semiconductor layer through the third semiconductor layer; and
a junction layer disposed through the third semiconductor layer to separate portions of the fourth semiconductor layer, the junction layer comprising a protruded portion of the second semiconductor layer, whereinat least two regions are formed in the power semiconductor device, and each of the regions is formed to have a different threshold voltage, andthe first gate electrode and the first, second, third, and fourth semiconductor layers comprise parts of a first transistor.
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Abstract
A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type having an effective impurity concentration that is less than an effective impurity concentration of the first semiconductor layer arranged on the first semiconductor layer, a third semiconductor layer of a second conductivity type arranged on the second semiconductor layer, and a gate electrode formed in the first second semiconductor layer and the third semiconductor layer, wherein at least two regions are formed in the power semiconductor device, and a threshold voltage of the first region is different from a threshold voltage of the second region.
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Citations
11 Claims
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1. A power semiconductor device, comprising:
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a first semiconductor layer having a first conductivity type; a second semiconductor layer having the first conductivity type disposed on the first semiconductor layer, the first semiconductor layer having an effective impurity concentration that is greater than an effective impurity concentration of the second semiconductor layer; a third semiconductor layer having a second conductivity type that is different from the first conductivity type; a fourth semiconductor layer comprising a plurality of semiconductor layers having the first conductivity type and the second conductivity type; a first gate electrode formed between adjacent semiconductor layers of the fourth semiconductor layer, the adjacent layers having the first conductivity type, and the first gate electrode extending to the second semiconductor layer through the third semiconductor layer; and a junction layer disposed through the third semiconductor layer to separate portions of the fourth semiconductor layer, the junction layer comprising a protruded portion of the second semiconductor layer, wherein at least two regions are formed in the power semiconductor device, and each of the regions is formed to have a different threshold voltage, and the first gate electrode and the first, second, third, and fourth semiconductor layers comprise parts of a first transistor. - View Dependent Claims (2, 3, 4, 5)
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6. A power semiconductor device, comprising:
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a drain electrode and a source electrode having a semiconductor portion disposed therebetween, wherein the semiconductor portion comprises; a drain layer having a first conductivity type; a drift layer having the first conductivity type disposed on the drain layer, the drain layer having an effective impurity concentration that is greater than an effective impurity concentration of the drift layer; a base layer having a second conductivity type that is different than the first conductivity type; a semiconductor layer comprising a plurality of source layers having the first conductivity type and a plurality of contact layers having the second conductivity type; a first gate electrode formed between adjacent source layers of the semiconductor layer, the first gate electrode extending to the drift layer through the base layer, wherein at least two regions are formed in the semiconductor portion with different effective impurity concentration of the base layer and the source layers, and the first gate electrode and the drain layer, the drift layer, the base layer, the source layers and the contact layers comprise parts of a first transistor; and a junction layer disposed through the base layer to separate portions of the source layers, the junction layer comprising a protruded portion of the second semiconductor layer. - View Dependent Claims (7, 8, 9, 10)
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11. A method for manufacturing a power semiconductor device, the method comprising:
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forming a first layer having a first conductivity type; forming a second layer on the first layer, the second layer having the first conductivity type, wherein the first layer has an effective impurity concentration that is greater than an effective impurity concentration of the second layer; forming a third layer on the second layer, the third layer having a second conductivity type that is different than the first conductivity type; forming a fourth layer comprising a plurality of semiconductor layers having the first conductivity type and the second conductivity type; forming a first transistor between adjacent semiconductor layers of the fourth layer, the adjacent layers having the first conductivity type, and the first gate electrode extending to the second layer through the third layer, wherein at least two regions are formed in the power semiconductor device, and each of the regions has a different threshold voltage; and forming a junction layer on the third layer, the junction layer comprising a protruded portion of the second semiconductor layer to form a second transistor.
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Specification