Channel Strain Control for Nonplanar Compound Semiconductor Devices

• US 20150380556A1
• Filed: 06/27/2014
• Published: 12/31/2015
• Est. Priority Date: 06/27/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng
• Granted Patent: US 9,502,565 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7849 the means being provided under the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A circuit device having differently-strained NMOS and PMOS FinFETs is provided. In an exemplary embodiment, a semiconductor device includes a substrate with a first fin structure and a second fin structure formed thereup. The first fin structure includes opposing source/drain regions disposed above a surface of the substrate; a channel region disposed between the opposing source/drain regions and disposed above the surface of the substrate; and a first buried layer disposed between the channel region and the substrate. The first buried layer includes a compound semiconductor oxide. The second fin structure includes a second buried layer disposed between the substrate and a channel region of the second fin structure, such that the second buried layer is different in composition from the first. For example, the second fin structure may be free of the compound semiconductor oxide.

Claims

1. A semiconductor device comprising:

a substrate; and

a fin structure formed on the substrate, wherein the fin structure includes;

opposing source/drain regions disposed above a surface of the substrate;

a channel region disposed between the opposing source/drain regions and disposed above the surface of the substrate; and

a buried layer disposed between the channel region and the substrate, wherein the buried layer includes a compound semiconductor oxide.

2. The semiconductor device of claim 1, wherein the buried layer includes a SiGe oxide.

3. The semiconductor device of claim 1, wherein the fin structure corresponds to an NMOS device.

4. The semiconductor device of claim 3, wherein the fin structure is a first fin structure, the semiconductor device further comprising:

a second fin structure that corresponds to a PMOS device and that includes a buried layer disposed between the substrate and a channel region of the second fin structure, wherein the buried layer of the second fin structure is different from the buried layer of the first fin structure.

5. The semiconductor device of claim 4, wherein the buried layer of the first fin structure includes a SiGe oxide, and wherein the buried layer of the second fin structure is free of the SiGe oxide.

6. The semiconductor device of claim 1, wherein the buried layer includes SiGe with a graded concentration of Ge with a lower concentration of Ge at a first portion closer to the substrate than at a second portion further from the substrate.

7. The semiconductor device of claim 6, wherein the graded concentration of Ge increases from about 20 atomic percent to about 60 atomic percent.

8. The semiconductor device of claim 1, wherein the opposing source/drain regions each include a seed layer disposed on the buried layer, and an epitaxial portion disposed on the seed layer.

9. The semiconductor device of claim 8, wherein the seed layer includes SiGe with a Ge concentration between about 20 atomic percent and about 70 atomic percent.

10. A semiconductor device comprising:

a substrate;

a NMOS FinFET formed on the substrate, wherein the NMOS FinFET includes;

a first insulator layer having a first composition and formed on the substrate; and

an n-channel region formed on the first insulator layer such that the first insulator layer electrically isolates the n-channel region from the substrate; and

a PMOS FinFET formed on the substrate, wherein the PMOS FinFET includes;

a second insulator layer formed on the substrate, wherein the second insulator layer has a second composition that is different from the first composition; and

a p-channel region formed on the second insulator layer such that the second insulator layer electrically isolates the p-channel region from the substrate.

11. The semiconductor device of claim 10, wherein the first insulator layer includes a SiGe oxide.

12. The semiconductor device of claim 11, wherein the second insulator layer is free of the SiGe oxide.

13. The semiconductor device of claim 11, wherein the first insulator layer includes a graded concentration of Ge that is lower in a portion of the first insulator layer closer to the substrate than in a portion of the first insulator layer further from the substrate.

14. The semiconductor device of claim 13, wherein the graded concentration increases from about 20 atomic percent to about 60 atomic percent.

15. The semiconductor device of claim 10, wherein the NMOS FinFET includes a source/drain structure adjacent the n-channel region, and wherein the source/drain structure includes a seed layer formed on the first insulating layer and an epitaxial structure disposed on the seed layer.

16. A method of fabricating a nonplanar circuit device, the method comprising:

receiving a workpiece having a first fin structure for a first device of a first type and a second fin structure for a second device of a second type, wherein each of the first fin structure and the second fin structure includes;

a buried layer disposed on a substrate and a semiconductor layer disposed on the buried layer;

based on the first device being of the first type, performing an oxidation process on the buried layer of the first fin structure;

epitaxially growing a source/drain feature of the first device in a source/drain region of the first fin structure; and

forming a gate structure of the first device over a channel region of the first fin structure.

17. The method of claim 16, wherein the oxidation process is configured to produce a tensile strain in the channel region of the first device.

18. The method of claim 16 further comprising:

based on the second device being of the second type, forming a mask layer over the second fin structure prior to the performing of the oxidation process.

19. The method of claim 16 further comprising:

forming a diffusion layer on the semiconductor layer of the first fin structure; and

performing an annealing process on the substrate to fuse the diffusion layer and the semiconductor layer of the first fin structure to form a fused layer.

20. The method of claim 19, wherein the forming of the gate structure includes forming the gate structure over a channel region of the fused layer;

and wherein the epitaxially growing of the source/drain feature includes;

recessing a source/drain portion of the fused layer to form a seed layer; and

epitaxially growing the source/drain feature on the seed layer.