Adaptive High-Order Nonlinear Function Approximation Using Time-Domain Volterra Series to Provide Flexible High Performance Digital Pre-Distortion
First Claim
1. A method for predistorting an input signal to compensate for non-linearities of an electronic device that operates on the input signal to produce an output signal, comprising:
- providing an input circuit for receiving a first input signal as a plurality of signal samples x[n] to be transmitted over a non-linear element;
providing one or more digital predistortion blocks coupled to the input circuit and generating an output signal y[n] by adaptively modifying the first input signal to compensate for distortion effects in the non-linear element, each digital predistortion block comprising;
a first delay line for storing a first plurality of signal samples x[n];
a second delay line for storing a first plurality of amplitude samples A[n] derived from the first plurality of signal samples x[n];
a plurality of Q predistorter cells, each comprising an input stage multiplier and multiplexer for combining amplitude samples received from the second delay line into a first stage output, a lookup table (LUT) connected to be addressed by the first stage output for generating an LUT output, and one or more output multiplication stages for combining the LUT output with signal samples and amplitude samples received from the first and second delay lines to generate an output signal sample yQ from said predistorter cell; and
an output adder circuit connected to combine the output signal samples yQ from the plurality of Q predistorter cells into a combined signal; and
processing the combined signal to generate the output signal y[n] for transmission to the non-linear element.
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Abstract
A method and apparatus are used to predistort input signal samples according to Volterra Series Approximation Model using one or more digital predistortion blocks (300) having a plurality of predistorter cells (301-303), each including an input multiplication stage (366-367) for combining absolute sample values received from an absolute sample delay line (362) into a first stage output, a lookup table (368) connected to be addressed by the first stage output for generating an LUT output, and a plurality of output multiplication stages (371-372, 373-374) for combining the LUT output with samples received from the amplitude sample delay line (362) and signal sample delay line (363) to generate an output signal sample yQ from said predistorter cell, where the output signal samples yQ from the predistorter cells are combined at an output adder circuit (375) to generate one or more Volterra terms of a combined signal (yOUT[n]).
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Citations
20 Claims
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1. A method for predistorting an input signal to compensate for non-linearities of an electronic device that operates on the input signal to produce an output signal, comprising:
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providing an input circuit for receiving a first input signal as a plurality of signal samples x[n] to be transmitted over a non-linear element; providing one or more digital predistortion blocks coupled to the input circuit and generating an output signal y[n] by adaptively modifying the first input signal to compensate for distortion effects in the non-linear element, each digital predistortion block comprising; a first delay line for storing a first plurality of signal samples x[n]; a second delay line for storing a first plurality of amplitude samples A[n] derived from the first plurality of signal samples x[n]; a plurality of Q predistorter cells, each comprising an input stage multiplier and multiplexer for combining amplitude samples received from the second delay line into a first stage output, a lookup table (LUT) connected to be addressed by the first stage output for generating an LUT output, and one or more output multiplication stages for combining the LUT output with signal samples and amplitude samples received from the first and second delay lines to generate an output signal sample yQ from said predistorter cell; and an output adder circuit connected to combine the output signal samples yQ from the plurality of Q predistorter cells into a combined signal; and processing the combined signal to generate the output signal y[n] for transmission to the non-linear element. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A circuit for predistorting a signal according to Volterra Series Approximation Model for transmission over a non-linear element, comprising:
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a first digital predistortion block comprising a first sample delay line for storing a plurality of first input signal samples x1[n];
a first vector magnitude computation unit for computing a plurality of first amplitude samples A1[n] derived from the plurality of first signal samples x1[n];
a first amplitude sample delay line for storing the plurality of first amplitude samples A1[n];
a first plurality of predistorter cells, each comprising an a first input stage for combining amplitude samples received from the first amplitude sample delay line into a first stage output, a first lookup table (LUT) connected to be addressed by the first stage output for generating a first LUT output, and one or more first output multiplication stages for combining the first LUT output with signal samples and amplitude samples received from the first sample delay line and first amplitude sample delay line to generate a first output signal sample yQ from said predistorter cell; and
a first output adder circuit connected to combine the first output signal samples yQ1 from the first plurality of predistorter cells into a first combined signal; anda second digital predistortion block comprising a second sample delay line for storing a plurality of second input signal samples x2[n];
a second vector magnitude computation unit for computing a plurality of second amplitude samples A2[n] derived from the plurality of second signal samples x2[n];
a second amplitude sample delay line for storing the plurality of second amplitude samples A2[n];
a second plurality of predistorter cells, each comprising an second input stage for combining amplitude samples received from the second amplitude sample delay line into a second stage output, a second lookup table (LUT) connected to be addressed by the second stage output for generating a second LUT output, and one or more second output multiplication stages for combining the second LUT output with signal samples and amplitude samples received from the second sample delay line and second amplitude sample delay line to generate a second output signal sample yQ2 from said predistorter cell; and
a second output adder circuit connected to combine the second output signal samples yQ2 from the second plurality of predistorter cells into a second combined signal;where the first and second digital predistortion blocks are connected in a cascaded arrangement to produce a type 2 or type 3 Volterra series cross term. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification