ADAPTIVE HIGH-ORDER NONLINEAR FUNCTION APPROXIMATION USING TIME-DOMAIN VOLTERRA SERIES TO PROVIDE FLEXIBLE HIGH PERFORMANCE DIGITAL PRE-DISTORTION

• US 20150381220A1
• Filed: 06/26/2015
• Published: 12/31/2015
• Est. Priority Date: 06/27/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Rashev, Peter Zahariev, Gal, Avraham Dov, Shor, Roi Menahem
• Granted Patent: US 9,628,119 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 1/3241 using predistortion circuits H03F1/3211, H03F1/3217 take precedence
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 2001/0425 with linearisation using predistortion

Abstract

A method is described for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal. The method comprises: providing an input for receiving a first input signal as a plurality of signal samples, x[n], to be transmitted over a non-linear element; providing at least one digital predistortion block comprising, a plurality of IQ predistorter cells coupled to the input, each comprising a lookup table (LUT) for generating an LUT output The at least one digital predistortion block block is configured to apply interpolation between LUT entries for the, plurality of LUTs; and generate an output signal, y[n], by each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries to compensate for distortion effects in the non-linear element. A combiner may be provided configured to combine the output signal samples, y_Q, from the plurality of IQ predistorter cells into a combined signal to generate the output signal, y[n], for transmission to the non-linear element. An error calculation block may be coupled to a digital predistortion adaptation block to determine and modify a predistortion performance.

Claims

1. A method for predistorting an input signal to compensate for non-linearities caused to the in'"'"' put signal in producing, an output signal, the method comprising:

providing an input for receiving a first input signal as a plurality of signal samples, to be transmitted over a non-linear element;

providing at least one digital predistortion block comprising a plurality of IQ predistorter cells coupled to the input, each IQ predistorter cell comprising a lookup table, LUT, for generating an LUT output, wherein the at least one digital predistortion block is configured to apply interpolation between LUT entries for the plurality of LUTs and generate an output signal from each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries; and

providing a combiner to combine the output signal from the plurality of IQ predistorter cells to generate the output signal for transmission to the non-linear element.

2. The method of claim 1, wherein:

providing at least one digital predistortion block configured to apply interpolation between LUT entries for the plurality of LUTs comprises providing at least one digital predistortion block configured to, apply interpolation between LUT entries for a plurality of multiple input line LUTs, and

providing at least one digital predistortion block configured to generate the output signal from each of the plurality of IQ predistorter cells comprises providing at, least one digital predistortion block configured to generate the output signal from each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated multiple input N line LUT entries.

3. The method of claim 1, wherein providing at least one digital predistortion block configured to apply interpolation between LUT entries for the plurality of LUTs comprises providing at least one digital predistortion block configured to apply multiple lines of interpolation between LUT entries for the plurality of LUTs.

4. The method of claim 1, further comprising providing a digital predistortion adaptation block coupled to the at least one digital predistortion block and configured to apply adaptation values to each of the plurality of LUTs based on a predistortion performance of the at least one digital predistortion block

5. The method of claim 4, further comprising providing at least one error calculation block coupled to the digital predistortion adaptation block and configured to apply predistortion error values to the digital predistortion adaptation block

6. The method of claim 5, wherein providing at least one error calculation block configured to apply adaptation values to the digital predistortion adaptation block comprises providing at least one error calculation block configured to apply adaptation values to the plurality of LUT entries per IQ predistorter cell using a plurality of lines of extrapolation.

7. The method of claim 6, wherein providing at least one error calculation block configured to apply adaptation values to the digital predistortion adaptation block comprises providing, at least one error calculation block configured to apply a linear update or secant update of adaptation values to the plurality of LUT entries per IQ predistorter cell.

8. The method of claim 5, wherein providing at least one error calculation block comprises:

providing a source path including a buffered delay line configured to route a modified version of the first input signal to the digital predistortion adaptation block;

, and

providing a receive error generation path configured to provide observation data on the predistortion performance of the at least one digital predistortion block to the error calculation block to support timing alignment of the adaptively modified first input signal and observation data thereof.

9. The method of claim 8 further comprising providing at least one filter in the receive error generation path.

10. The method of claim 8 further comprising providing at least one filter n the source path both before and after the buffered delay line.

12. The method of claim 1, wherein providing at least one digital predistortion blocks comprises:

providing a first digital predistortion block configured to generate at least one static Volterra polynomial term;

providing a second digital predistortion block configured to generate at east one dynamic Volterra memory polynomial term;

providing a third digital predistortion block configured to generate at least one type-1 Volterra cross-term; and

providing at least one fourth digital predistortion block configured to generate at least one type-2 or type-3 Volterra cross-term.

13. The method of claim 12, wherein providing at least one fourth digital predistortion block comprises providing a plurality of cascaded digital predistortion blocks that are connected together and configured to generate second order type-2 or type-3 Volterra cross-terms.

14. The method of claim 1, wherein providing the input comprises providing a multiplexer for selecting between the first input signal and a second input signal of a plurality of delayed signal samples.

15. The method of claim 1, further comprising providing a memory coupled to the at least one digital predistortion block and configured to store a result from applying interpolation between LUT entries for the plurality of LUTs, for use by an indirect digital predistortion model.

11. The method of claim L wherein providing at least one digital predistortion block configured to apply interpolation between LUT entries for the plurality of LUTs includes providing at least one digital predistortion block configured to apply a different decay factor per digital predistortion block.

16. An integrated circuit for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an output signal, the integrated circuit comprising:

an input for receiving a first input signal as a plurality of signal samples to be transmitted over a non-linear element;

at least one digital predistortion block comprising a plurality of IQ predistorter cells coupled to the input, each IQ predistorter cell comprising a lookup table (LUT) for generating an LUT output, and configured to;

apply interpolation between LUT entries for the plurality of LUTs, and

generate an output signal from each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries.

17. The integrated circuit of claim 16, wherein the at least one digital predistortion block is configured to apply interpolation between LUT entries for a plurality of multiple input line LUTs and generate an output signal from each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated multiple input line LUT entries.

18. The integrated circuit of claim 16, wherein the at least one digital predistortion block is configured to apply multiple lines of interpolation between LUT entries for the plurality of LUTs.

19. The integrated circuit of claim 16, further comprising a digital predistortion adaptation block coupled to the plurality of IQ predistorter cells and configured to apply adaptation values to each of the plurality of LUTs based on a predistortion performance of the at least one digital predistortion block.

20. An electronic device comprising:

anon-linear circuit;

a processor circuit, coupled to the non-linear circuit, configured to predistort an input signal to compensate for non-linearities caused to the input signal in producing an output signal, wherein the processor circuit comprises;

an input for receiving a first input signal as a plurality of signal samples to be transmitted over a non-linear element;

at least one digital predistortion block comprising a plurality of IQ predistorter cells coupled to the input;

each IQ predistorter cell comprising a lookup table (LUT) for generating an LUT output and configured to;

apply interpolation between LUT entries for the plurality of LUTs;

generate an output signal from each of the plurality of IQ predistorter cells by adaptively modifying the first input signal using interpolated LUT entries; and

a combiner coupled to the processor circuit and configured to combine the output signal from each of the plurality of IQ predistorter cells into an output signal for transmission to the non-linear element.