SEGMENTED DIGITAL-TO-TIME CONVERTER CALIBRATION

• US 20150381337A1
• Filed: 06/30/2014
• Published: 12/31/2015
• Est. Priority Date: 06/30/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Madoglio, Paolo, Palaskas, Georgios, Pellerano, Stefano, Ravi, Ashoke, Chandrashekar, Kailash
• Granted Patent: US 9,209,958 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H04B 17/14 of the whole transmission and reception path, e.g. self-test loop-back
• CPC Class Codes: H04B 17/21 for calibration; for correcting measurements
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection

Abstract

This application discusses, among other things, calibration systems for ameliorating nonlinearity of a digital-to-time converter (DTC). In an example, a calibration system can include a calibration path configured to represent a segment of the DTC, a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment, and a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the DTC using the timing error information.

Claims

1. A calibration circuit for a segmented digital-to-time converter (DTC), the segmented DTC configured to receive reference frequency information and to provide processed frequency information, the calibration circuit comprising:

a calibration path configured to represent a segment of the segmented DTC;

a time-to-digital circuit configured to receive an output of the calibration path and the processed frequency information and to provide timing error information of the segment;

a calibration engine configured to receive controller modulation information from a main controller, to provide calibration modulation information to the segmented DTC, to receive the timing error information, and to provide compensation information to a correction circuit coupled to the segmented DTC using the timing error information.

2. The calibration circuit of claim 1, including a switch having a first state and a second state, the first state of the switch configured to provide the controller modulation information to the segmented DTC and to isolate the segmented DTC from the calibration modulation information.

3. The calibration circuit of claim 2, wherein the second state of the switch is configured to isolate the controller modulation information from the segmented DTC and to provide the calibration modulation information to the segmented DTC.

4. The calibration circuit of claim 3, wherein the calibration path includes a representation of a delay element of the segmented DTC;

wherein the calibration engine, during a first stage of a first foreground calibration, is configured to;

provide first coarse modulation information to a coarse stage of the segmented DTC;

provide first fine modulation information to a fine stage of the segmented DTC and to the calibration path; and

provide adjustment information to the calibration path using the timing error information to reduce transition errors between output information of the segmented DTC and output information of the calibration path.

5. The calibration circuit of claim 4, wherein the calibration engine, during a second stage of the first foreground calibration, is configured to:

provide second coarse modulation information to the coarse stage of the segmented DTC;

continue to provide the adjustment information to the calibration path;

provide second fine modulation information to the fine stage of the segmented DTC to align the output of the segmented DTC with the output of the calibration path; and

subtract the second fine modulation information from the first fine modulation information to identify a first coarse delay interval.

6. The calibration circuit of claim 5, wherein the calibration circuit is configured to couple to a DTC including a fine stage edge interpolator,

wherein the calibration path includes an extra delay element configured to provide a predetermined extra delay during the second stage of the first foreground calibration;

wherein the calibration engine is configured to add the extra delay element of the calibration path to the delay of the calibration path during the second stage of the first foreground calibration, and to not add the extra delay element of the calibration path to the delay of the calibration path during the first stage of the first foreground calibration.

7. The calibration circuit of claim 5, wherein, for each coarse setting of the coarse stage of the segmented DTC, the calibration engine is configured to repeat the first stage and the second stage of the first foreground calibration and to provide coarse delay interval information for each coarse setting to the correction circuit.

8. The calibration circuit of claim 4, wherein, during a second foreground calibration configured to execute after completion of the first foreground calibration, the calibration engine is configured to provide a first change of the coarse setting in a first direction followed by a second change in an opposite direction;

to measure an alignment error between the output of the fine stage and the output of the calibration path after the second change in the opposite direction; and

to provide correction information for adjusting the alignment error to the correction circuit.

9. The calibration circuit of claim 2, wherein the calibration engine, during the first state of the switch, is configured:

to set the calibration path to a first state indicative of a coarse delay interval and a minimum fine delay interval of the segmented DTC;

to identify first fine modulation information within the modulation information, the first fine modulation information configured to establish a maximum delay of the fine stage; and

to enable the time-to-digital circuit to provide drift error information corresponding to a difference between a output transition of the calibration path and a corresponding output transition of the segmented DTC.

10. The calibration circuit of claim 9, wherein the calibration engine is configured to disable the time-to-digital circuit after receiving the drift error information.

11. The calibration circuit of claim 9, wherein the calibration engine is configured to provide a representation of the drift error information to the correction circuit.

12. The calibration circuit of claim 1, wherein the calibration path includes a ring oscillator.

13. A method of calibrating a segmented digital-to-time converter (DTC), the method comprising:

receiving modulation information at a calibration engine of a calibration circuit from a main controller;

providing calibration modulation information to the segmented DTC and a calibration path of the calibration circuit from the calibration engine, the calibration path configured to represent the a segment of the segmented DTC;

receiving an output of the DTC at a time-to-digital circuit;

receiving an output of the calibration path at the time to digital circuit;

providing timing error information of the segment to the calibration engine using the output of the DTC and the output of the calibration path; and

providing compensation information to a correction circuit coupled to the segmented DTC using the timing error information and the calibration engine.

14. The method of claim 13, including providing the calibration modulation information to the segmented DTC using a first state of a switch of the calibration circuit;

and

isolating the segmented DTC from the controller modulation information using the first state of the switch.

15. The method of claim 14, including executing a first stage of a first foreground calibration using the calibration engine, wherein executing the first foreground calibration includes:

providing first coarse modulation information to a coarse stage of the segmented DTC;

providing first fine modulation information to a fine stage of the segmented DTC;

measuring transition errors of the calibration path using the output of the time-to-digital circuit; and

adjusting calibration path modulation information to the calibration path to reduce transition errors between output information of the segmented DTC and output information of the calibration path.

16. The method of claim 15, including executing a second stage of the first foreground calibration after completion of the first stage, wherein the second stage includes:

providing second coarse modulation information to the coarse stage of the segmented DTC;

providing the adjusted calibration path modulation information to the calibration path;

providing second fine modulation information to the fine stage of the segmented DTC to align the output of the segmented DTC with the output of the calibration path; and

subtracting the second fine modulation information from the first fine modulation information using the calibration engine to identify a first coarse delay interval.

17. The method of claim 16, wherein the calibration circuit is configured to couple to a DTC including a fine stage edge interpolator, the method including:

enabling an extra delay element configured to provide an additional predetermined extra delay to the calibration path during the second stage of the first foreground calibration;

disabling the extra delay element of the calibration path during the first stage of the first foreground calibration.

18. The method of claim 16, including repeating the first and second stage of the first foreground calibration for each coarse setting of the coarse stage of the segmented DTC using the calibration engine;

and

providing coarse delay interval information for each coarse setting to the correction circuit.

19. The method of claim 15, including executing a second foreground calibration after completion of the first foreground calibration, wherein the second foreground calibration includes:

providing a first change of the coarse setting in a first direction to the coarse stage followed by second change in an opposite direction of the first change using the calibration engine;

measuring an alignment error between the output of the DTC and the output of the calibration path after the second change using the time-to-digital circuit; and

providing dynamic correction information for adjusting the alignment error from the calibration engine to the correction circuit using the alignment error.

20. The method of claim 13, including providing the controller modulation information to the segmented DTC using a second state of the switch;

and

isolating the segmented DTC from the calibration modulation information using the first state of the switch.

21. The method of claim 20, including executing a background calibration using the calibration engine, wherein executing the background calibration includes:

setting the calibration path to a first state representative of a first delay of the fine stage of the segmented DTC;

identifying first fine modulation information within the controller modulation information using the calibration engine, the first fine modulation information configured to establish the first delay of the fine stage;

enabling the time-to-digital circuit using the calibration engine; and

receiving drift error information corresponding to the first delay of the fine stage at the calibration engine from the time-to-digital circuit.

22. The method of claim 21, wherein executing a background calibration includes providing a representation of the drift error information corresponding to the first delay of the fine stage to the correction circuit from the calibration engine.

23. The method of claim 21, wherein executing a background calibration includes disabling the time-to-digital circuit after receiving the drift error information corresponding to the first delay of the fine stage.