CRYPTOGRAPHIC PROCESSOR, METHOD FOR IMPLEMENTING A CRYPTOGRAPHIC PROCESSOR AND KEY GENERATION CIRCUIT

• US 20150381351A1
• Filed: 06/27/2014
• Published: 12/31/2015
• Est. Priority Date: 06/27/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kuenemund, Thomas, Gammel, Berndt, Klug, Franz
• Granted Patent: US 9,806,881 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: H04L 2209/046 of operations, operands or results of the operations
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC

Abstract

A cryptographic processor is described comprising a processing circuit configured to perform a round function of an iterated cryptographic algorithm, a controller configured to control the processing circuit to apply a plurality of iterations of the round function on a message to process the message in accordance with the iterated cryptographic algorithm and a transformation circuit configured to transform the input of a second iteration of the round function following a first iteration of the round function of the plurality of iterations and to supply the transformed input as input to the second iteration wherein the transformation circuit is implemented using a circuit camouflage technique.

Claims

1. A cryptographic processor comprising:

a processing circuit configured to perform a round function of an iterated cryptographic algorithm;

a controller configured to control the processing circuit to apply a plurality of iterations of the round function on a message to process the message in accordance with the iterated cryptographic algorithm;

a transformation circuit configured to transform the input of a second iteration of the round function following a first iteration of the round function of the plurality of iterations and to supply the transformed input as input to the second iteration;

wherein the transformation circuit is implemented using a circuit camouflage technique.

2. The cryptographic processor according to claim 1, wherein the iterated cryptographic algorithm is an iterated encryption algorithm or an iterated decryption algorithm or an iterated hash construction.

3. The cryptographic processor according to claim 1, wherein the iterated cryptographic algorithm is an iterated block cipher algorithm for encryption or decryption.

4. The cryptographic processor according to claim 1, wherein the input of the second iteration is the intermediate state of a message processed by the first iteration.

5. The cryptographic processor according to claim 1, wherein the input of the second iteration is a cryptographic key for encrypting or decrypting a message.

6. The cryptographic processor according to claim 1, wherein the transformation circuit is configured to transform the input of each of a plurality of iterations of the round function following the first iteration and to supply the transformed input as input to the second iteration.

7. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises the transformation circuit being implemented to include at least one circuit structure with a hidden logic function.

8. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises the transformation circuit being implemented to include circuit structures to hamper reverse engineering of the transformation circuit.

9. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises the transformation circuit being implemented to include at least one dummy circuit structure.

10. The cryptographic processor according to claim 9, wherein the transformation of the input of the second iteration is independent from the logic state of the dummy circuit structure.

11. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises the transformation circuit being implemented to include a circuit structure which comprises one or more switching elements but has an output with a logic value that is independent from the input of the second iteration.

12. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises the transformation circuit being implemented to include a field effect transistor which is configured to have a constant switch state.

13. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises the transformation circuit being implemented to include a hidden connection in a diffusion layer or a polysilicon layer.

14. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises the transformation circuit being implemented to comprise cells with different logic functions but similar layout.

15. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises forming a circuit structure of the transformation circuit by

forming two field effect transistors;

connecting the field effect transistors such that an output signal of the digital circuit in response to a predetermined input signal has an undefined logic state when the threshold voltages of the field effect transistors are equal; and

setting the threshold voltages of at least one of the field effect transistors such that the output signal of the digital circuit in response to the predetermined input signal has a predetermined defined logic state.

16. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises the transformation circuit being implemented to include a sub-circuit comprising

at least one p channel field effect transistor;

at least one n channel field effect transistor;

a first power supply terminal configured to receive a first supply voltage with an upper supply potential; and

a second power supply terminal configured to receive a second supply voltage with a lower supply potential;

wherein the at least one p channel field effect transistor and the at least one n channel field effect transistor are connected such that

the at least one n channel field effect transistor, if supplied with the upper supply potential at its gate, supplies the lower supply potential to the gate of the at least one p channel field effect transistor; and

the at least one p channel field effect transistor, if supplied with the lower supply potential at its gate, supplies the upper supply potential to the gate of the at least one n channel field effect transistor;

wherein the sub-circuit is configured such that the logic state of the gate of the at least one p channel field effect transistor and the logic state of the gate of the at least one n channel field effect transistor can only be changed by changing a supply of at least one of the first supply voltage and the second supply voltage to the sub-circuit; and

a connection coupled to the gate of the at least one p channel field effect transistor or the gate of the at least one n channel field effect transistor and a further component of the transformation circuit.

17. The cryptographic processor according to claim 1, wherein the transformation circuit being implemented using a circuit camouflage technique comprises the transformation circuit being implemented to include a sub-circuit comprising

a plurality of supply lines delimiting a plurality of cell areas;

and

a gate comprising a first transistor and a second transistor, wherein the first transistor is located in a first cell area of the plurality of cell areas and the second transistor is located in a second cell area of the plurality of cell areas such that a supply line of the plurality of supply lines lies between the first cell area and the second cell area.

18. A method for implementing a cryptographic processor comprising:

forming a processing circuit configured to perform a round function of an iterated cryptographic algorithm;

forming a controller configured to control the processing circuit to apply a plurality of iterations of the round function on a message to process the message in accordance with the iterated cryptographic algorithm;

forming a transformation circuit configured to transform the input of a second iteration of the round function following a first iteration of the round function of the plurality of iterations and to supply the transformed input as input to the second iteration;

wherein the transformation circuit is formed using a circuit camouflage technique.

19. A key generation circuit comprising

a plurality of circuits, wherein each circuit is configured to output a respective predetermined output value in response to a respective predetermined input and wherein the plurality of circuits are implemented using a circuit camouflage technique;

a controller configured to supply, for each circuit of the plurality of circuits, the predetermined input to the circuit and to derive a cryptographic key from the output values of the circuits.

20. The key generation circuit according to claim 19, wherein the predetermined output value is an output bit.

21. The key generation circuit according to claim 19, wherein the derivation of the key from the outputs comprises a permutation of the output values of the circuits.

22. The key generation circuit according to claim 19, wherein the derivation of the key from the output comprises a Boolean combination of the output values.

23. The key generation circuit according to claim 19, wherein the controller is configured to supply the input signals to at least two of the circuits at different time periods.

24. The key generation circuit according to claim 19, wherein each circuit is configured to output a further predetermined output value when the circuit is not supplied with the predetermined input.

25. The key generation circuit according to claim 19, wherein the controller is configured to derive the cryptographic key from the output values of the circuits and at least a part of the further output values of the circuits.