RADIO FREQUENCY PEAK DETECTION WITH SUBTHRESHOLD BIASING

• US 20160004265A1
• Filed: 07/01/2014
• Published: 01/07/2016
• Est. Priority Date: 07/01/2014
• Status: Active Grant

• Current Assignee: Innophase, Inc.
• Original Assignee: Innophase, Inc.
• Inventors: Testi, Nicolo, Li, Xi, Xu, Yang
• Granted Patent: US 9,229,460 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 1/46 wherein the variable actually regulated by the final control device is dc G05F1/625 takes precedence

Abstract

A radio-frequency peak amplitude detection circuit includes a load capacitor, a current source that charges the load capacitor and set the bias current for the field effect transistors, and a pair of field effect transistors. The gates of the field effect transistors are biased at a level below the threshold voltage of the transistors. The transistors are arranged in parallel with the capacitor and are operable to drain the capacitor at a rate determined by a differential input at the gates of the transistors. The voltage across the load capacitor is low-pass filtered and has a voltage level representative of the amplitude of the differential input signal.

Claims

1. A circuit comprising:

a load capacitor;

a first and a second field effect transistor, each transistor having a channel and a gate, the gate of the first transistor being coupled to a first input node and the gate of the second transistor being coupled to a second input node, the channels of the first and second field effect transistors being arranged in parallel with the load capacitor;

a first current source operative to charge the load capacitor and to set a bias current for the field effect transistors;

a low-pass filter connected between the load capacitor and an output node; and

a biasing circuit connected to the gates of the first and second transistors, the biasing circuit being operative to provide a biasing voltage lower than a threshold voltage of the first and second transistors.

2. The circuit of claim 1, wherein the biasing circuit comprises:

a third and a fourth field effect transistor, each transistor having a channel and a gate;

a bias output node connected to the gates of the first, second, third, and fourth transistors;

a second current source operative to supply a current to the channels of the third and fourth transistors; and

a comparator circuit operative to apply a voltage to the bias output node, the comparator circuit being responsive to a voltage level across the channels of the third and fourth transistors.

3. The circuit of claim 2, wherein the comparator circuit comprises a differential operational amplifier having a first amplifier input connected to a reference voltage source and a second amplifier input connected between the second current source and channels of the third and fourth transistors.

4. The circuit of claim 3, wherein the first amplifier input is an inverting input and the second amplifier input is a non-inverting input.

5. The circuit of claim 1, wherein each of the transistor channels has a first end and a second end, and the load capacitor has a first terminal and a second terminal, wherein:

the first ends of the channels and the first terminal of the load capacitor are connected to a common node; and

the second ends of the channels and the second terminal of the load capacitor are connected to ground.

6. The circuit of claim 5, wherein the current source is connected to the common node.

7. The circuit of claim 5, wherein the first ends of the channels are drain terminals of the respective transistors and the second ends of the channels are source terminals of the respective transistors.

8. The circuit of claim 1, wherein the low-pass filter is an RC filter comprising a series resistor and a parallel capacitor.

9. The circuit of claim 1, wherein the first and second field-effect transistors are insulated-gate field-effect transistors.

10. The circuit of claim 1, wherein the biasing circuit is connected to the gates of the first and second transistors through respective first and second bias resistors.

11. The circuit of claim 1, wherein the gate of the first transistor is coupled to the first input node through a first capacitive coupling and the gate of the second transistor is coupled to the second input node through a second capacitive coupling.

12. The circuit of claim 1, wherein the first and a second field effect transistors have matched characteristics.

13. A circuit comprising:

a peak detection circuit including a first and a second field effect transistor, each transistor having a gate coupled to a respective input node;

a biasing circuit having a bias output node connected to the gates of the first and second transistors, the biasing circuit being operative to provide a biasing voltage lower than a threshold voltage of the first and second transistors, the biasing circuit further comprising;

a third and a fourth field effect transistor, each transistor having a channel and a gate, the gates of the third and fourth field effect transistors being connected to the bias output node;

a current source operative to supply a current to the channels of the third and fourth transistors; and

a comparator circuit operative to apply a voltage to the bias output node, the comparator circuit being responsive to a voltage level across the channels of the third and fourth transistors.

14. The circuit of claim 13, wherein the comparator circuit comprises a differential operational amplifier having a first amplifier input connected to a reference voltage source and a second amplifier input connected between the second current source and channels of the third and fourth transistors.

15. The circuit of claim 14, wherein the first amplifier input is an inverting input and the second amplifier input is a non-inverting input.

16. A method comprising:

charging a load capacitor;

discharging the load capacitor through a first channel of a first field effect transistor and a second channel of a second field effect transistor;

biasing a gate of the first field effect transistor and a gate of the second field effect transistor at a bias voltage below a threshold voltage of the first field effect transistor and the second field effect transistor;

applying a differential input signal at the gate of the first field effect transistor and the gate of the second field effect transistor; and

low-pass filtering a voltage across the load capacitor to generate an output signal.

17. The method of claim 16, wherein the biasing comprises:

supplying a current to a channels of a third field-effect transistor and a channel of a fourth field-effect transistor;

generating a biasing voltage based on a voltage across the channels of the third and fourth transistors; and

providing the biasing voltage to the gates of the first and the second field effect transistor.

18. The method of claim 17, wherein the generating of the biasing voltage comprises:

comparing the voltage across the channels of the third and fourth transistors with a reference voltage; and

adjusting the biasing voltage such that the voltage across the channels of the third and fourth transistors matches the reference voltage.

19. The method of claim 18, wherein the adjusting of the biasing voltage comprises:

increasing the biasing voltage in response to a determination that the voltage across the channels of the third and fourth transistors is higher than the reference voltage; and

decreasing the biasing voltage in response to a determination that the voltage across the channels of the third and fourth transistors is lower than the reference voltage.

20. The method of claim 16, wherein the input signal is a radio frequency signal.