STORAGE DEVICE INCLUDING NONVOLATILE MEMORY AND MEMORY CONTROLLER, AND OPERATING METHOD OF STORAGE DEVICE

• US 20160004438A1
• Filed: 07/02/2015
• Published: 01/07/2016
• Est. Priority Date: 07/02/2014
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KWON, MOONSANG, KIM, KYUNG HO, OH, MOONWOOK, MOON, SANGKWON
• Application Number:
  US14/790,342
• Publication Number:
  US 20160004438A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

An operation method of a storage device includes receiving quality of service (QoS) information of a plurality of virtual channels and storing the QoS information. A nonvolatile memory is accessed using different schemes according to the stored QoS information and commands received by virtual channels. The virtual channels are channels through which the storage device communicates with an external device.

Claims

1. An operation method of a storage device including a nonvolatile memory and a memory controller configured to control the nonvolatile memory, the method comprising:

receiving quality of service (QoS) information of a plurality of virtual channels;

storing the QoS information; and

accessing the nonvolatile memory using different schemes according to the stored QoS information and commands being received from the virtual channels, wherein

the plurality of virtual channels are channels through which the storage device communicates with an external device.

2. The operation method of claim 1, wherein:

the memory controller comprises a plurality of register sets corresponding to the plurality of virtual channels respectively,

the memory controller is configured to communicate with the external device through one input/output channel, and

each register set forms one virtual channel together with the one input/output channel.

3. The operation method of claim 2, wherein the accessing the nonvolatile memory using different schemes comprises:

distinguishing which virtual channel, among the plurality of virtual channels, a command is received through depending on which register set, among the register sets, the command is received through;

selecting an access scheme according to the distinguished virtual channel and a QoS corresponding to the distinguished virtual channel, the QoS being obtained from the QoS information; and

accessing the nonvolatile memory according to the selected access scheme.

4. The operation method of claim 1, wherein:

addresses of the nonvolatile memory are divided to be assigned to the plurality of virtual channels respectively, and

the accessing the nonvolatile memory using different schemes comprises;

distinguishing which virtual channel, among the virtual channels, a command is received through according to an address being received from the external device together with the command, the address corresponding to one of the plurality of virtual channels;

selecting an access scheme according to the distinguished virtual channel and a QoS corresponding to the distinguished virtual channel, the QoS being obtained from the QoS information; and

accessing the nonvolatile memory according to the selected access scheme.

5. The operation method of claim 1, wherein the accessing the nonvolatile memory using different schemes comprises:

performing a write operation of a first scheme with respect to the nonvolatile memory according to a first write command from a first virtual channel where a first QoS is required; and

performing a write operation of a second scheme with respect to the nonvolatile memory according to a second write command from a second virtual channel where a second QoS lower than the first QoS is required.

6. The operation method of claim 5, wherein a write speed of the first scheme is faster than a write speed of the second scheme.

7. The operation method of claim 5, wherein a degree that the nonvolatile memory is deteriorated according to the write operation of the second scheme is smaller than a degree that the nonvolatile memory is deteriorated according to the write operation of the first scheme.

8. The operation method of claim 1, wherein:

the storage device further comprises a buffer memory configured to store data to be written in the nonvolatile memory and data being read from the nonvolatile memory, and

the accessing the nonvolatile memory using different schemes comprises;

dividing a storage space of the buffer memory to assign the divided storage spaces to the plurality virtual channels respectively according to the QoS information; and

accessing the nonvolatile memory according to the commands using the storage spaces assigned to the plurality virtual channels respectively.

9. The operation method of claim 1, wherein:

the memory controller is configured to manage a command queue configured to store the commands,

the accessing the nonvolatile memory using different schemes comprises dividing slots of the command queue to generate a plurality of virtual command queues corresponding to the virtual channels respectively, and

queue depths of the plurality of virtual command queues are controlled according to the QoS information.

10. The operation method of claim 1, wherein:

the memory controller is configured to manage a command queue configured to store the commands,

the accessing the nonvolatile memory using different schemes comprises dividing slots of the command queue to generate a plurality of virtual command queues corresponding to the virtual channels respectively, and

the frequency that each of the command queues is selected and thereby a command is performed is controlled according to the QoS information.

11. The operation method of claim 1, wherein:

the memory controller is configured to manage a command queue configured to store the commands, and

the accessing the nonvolatile memory using different schemes comprises;

enqueuing the commands in the command queue; and

scheduling the commands enqueued in the command queue according to the QoS information.

12. The operation method of claim 11, wherein

a maximum delay time that the commands enqueued in the command queue are delayed by the scheduling is differently set according to the QoS information.

13. The operation method of claim 1, wherein:

the memory controller is configured to manage a command queue configured to store the commands, and

the accessing the nonvolatile memory using different schemes comprises;

selecting activation channels among the channels according to the QoS information; and

accessing the nonvolatile memory using the selected activation channels.

14. The operation method of claim 1, wherein:

the memory controller is configured to manage a command queue configured to store the commands, and

the accessing the nonvolatile memory using different schemes comprises;

selecting a first command from the command queue; and

performing the first command according to a second QoS in the case that the second QoS of a second command subsequent to the first command is higher than a first QoS of the first command, and performing the first command according to the first QoS in the case that the second QoS is not higher than the first QoS.

15. (canceled)

16. A method of accessing a nonvolatile memory executed by a memory controller, the method comprising:

receiving quality of service (QoS) information and a command corresponding to each of a plurality of virtual machines;

allocating a resource for supporting each virtual machine in accordance with the corresponding QoS information; and

accessing, with each of the virtual machines, the nonvolatile memory according to the corresponding command and using the allocated resource.

17. The method of claim 16, wherein the allocated resource is a speed that data is written to the nonvolatile memory.

18. The method of claim 16, wherein the allocated resource is a scheduling priority for accessing the nonvolatile memory.

19. The method of claim 16, wherein the allocated resource is random access memory assigned to each of the virtual machines.

20. The method of claim 16, wherein the allocated resource is one or more communication channels between the memory controller and the nonvolatile memory.

21-24. -24. (canceled)

25. An operating method of a storage device including a nonvolatile memory and a memory controller, the operating method comprising:

detecting reception of a command at one register of a plurality of registers, the plurality of registers having quality of service (QoS) information respectively;

selecting an access according to the command and a QoS information assigned to one register; and

accessing the nonvolatile memory according to the selected access scheme.