CACHING SYSTEMS AND METHODS WITH SIMULATED NVDRAM

• US 20160004465A1
• Filed: 07/16/2014
• Published: 01/07/2016
• Est. Priority Date: 07/03/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Sampathkumar, Kishore Kaniyar, Purkayastha, Saugata Das
• Granted Patent: US 10,191,855 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list

Abstract

Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD. The DRAM and the SSD are also sectioned into pages and mapped to pages of the host memory. A host processor is operable to generate Input/Output (I/O) requests. An HBA driver is operable to process the I/O requests. The HBA driver is also operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.

Claims

1. A system, comprising:

a host processor operable to generate Input/Output (I/O) requests;

a host memory communicatively coupled to the host processor and sectioned into pages;

a host bus adapter (HBA) communicatively coupled to the host processor to process the I/O requests, wherein the HBA comprises a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD); and

an HBA driver operable on the host processor

wherein the DRAM is sectioned into pages mapped to pages of the host memory, and the SSD is sectioned into pages mapped to pages of the DRAM, and

wherein the HBA driver is operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.

2. The system of claim 1, wherein:

the HBA driver is further operable to adaptively update the rate of page reclamation based on the detection.

3. The system of claim 2, wherein:

the HBA driver is further operable to adaptively update the rate of page reclamation by changing a distance between journal entry markers in the DRAM based on a rate at which the pages of the DRAM are accessed.

4. The system of claim 1, wherein:

the detection is based on a Most Recently Used (MRU) page replacement policy.

5. The system of claim 1, wherein:

the HBA driver is further operable to process the I/O requests through a storage protocol stack, and to run as background processing to perform the detection, the determination of the rate of page reclamation, and the page reclamation outside of the storage protocol stack.

6. The system of claim 1, further comprising:

an operating system operable to direct the processor to generate a page fault when the an application running on host processor attempts to load the page of data into the DRAM and determines that the data is not in the DRAM.

7. The system of claim 1, wherein:

the SSD maintains data of the DRAM during a power outage.

8. A method operable in a host system comprising a host processer, a host memory, a host bus adapter (HBA), and an HBA driver operable on the host processor, the HBA comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD), the method comprising:

sectioning the host memory into pages;

sectioning the DRAM into pages;

sectioning the SSD into pages;

mapping the host memory pages to the DRAM pages;

mapping the pages of the DRAM to the pages of the SSD to provide the host processor with direct access to the pages of the SSD through the DRAM;

detecting when the pages of the DRAM are accessed;

determining a rate of page reclamation based on the detection; and

replacing pages of data in the DRAM by loading pages of data from the SSD into the pages of the DRAM based on the determined rate of page reclamation.

9. The method of claim 8, further comprising:

adaptively updating the rate of page reclamation based on the detection.

10. The method of claim 9, wherein:

adaptively updating the rate of page reclamation by changing a distance between journal entry markers in the DRAM based on a rate at which the pages of the DRAM are accessed.

11. The method of claim 8, wherein:

detecting is based on a Most Recently Used (MRU) page replacement policy.

12. The method of claim 8, further comprising:

processing the I/O requests through a storage protocol stack of the host system; and

running a driver via background processing to perform said detecting, said determining, and said replacing outside of the storage protocol stack.

13. The method of claim 8, further comprising:

generating a page fault when an application attempts to load the page of data into the DRAM and determines that the data is not in the DRAM.

14. The method of claim 8, wherein:

the SSD maintains data of the DRAM during a power outage.

15. A non-transitory computer readable medium comprising instructions that, when directed by a processor in a host system comprising a host memory, a host bus adapter (HBA), and an HBA driver, the HBA comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD), direct the processor to:

section the host memory into pages;

section the DRAM into pages;

section the SSD into pages;

map the host memory pages to the DRAM pages;

map the pages of the DRAM to the pages of the SSD to provide the host processor with direct access to the pages of the SSD through the DRAM;

detect when the pages of the DRAM are accessed;

determine a rate of page reclamation based on the detection; and

reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.

16. The computer readable medium of claim 15, further comprising instructions that direct the processor to:

adaptively update the rate of page reclamation based on the detection.

17. The computer readable medium of claim 16, further comprising instructions that direct the processor to:

adaptively update the rate of page reclamation by changing a distance between journal entry markers in the DRAM based on a rate at which the pages of the DRAM are accessed.

18. The computer readable medium of claim 15, further comprising instructions that direct the processor to:

detect when the pages of the DRAM have been accessed based on a Most Recently Used (MRU) page replacement policy.

19. The computer readable medium of claim 15, further comprising instructions that direct the processor to:

process the I/O requests through a storage protocol stack of the host system; and

run a driver as background processing to perform said detecting, said determining, and said replacing outside of the storage protocol stack.

20. The computer readable medium of claim 15, further comprising instructions that direct the processor to:

generate a page fault when an application running on the processor attempts to load the page of data into the DRAM and determines that the data is not in the DRAM.