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CACHING SYSTEMS AND METHODS WITH SIMULATED NVDRAM

  • US 20160004465A1
  • Filed: 07/16/2014
  • Published: 01/07/2016
  • Est. Priority Date: 07/03/2014
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • a host processor operable to generate Input/Output (I/O) requests;

    a host memory communicatively coupled to the host processor and sectioned into pages;

    a host bus adapter (HBA) communicatively coupled to the host processor to process the I/O requests, wherein the HBA comprises a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD); and

    an HBA driver operable on the host processorwherein the DRAM is sectioned into pages mapped to pages of the host memory, and the SSD is sectioned into pages mapped to pages of the DRAM, andwherein the HBA driver is operable to detect when the pages of the DRAM are accessed, to determine a rate of page reclamation based on the detection, and to reclaim pages of data in the DRAM by moving pages of data from the DRAM into the pages of the SSD based on the determined rate of page reclamation.

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