METHOD OF OPERATING A MULTI-THREAD CAPABLE PROCESSOR SYSTEM, AN AUTOMOTIVE SYSTEM COMPRISING SUCH MULTI-THREAD CAPABLE PROCESSOR SYSTEM, AND A COMPUTER PROGRAM PRODUCT

• US 20160004535A1
• Filed: 02/15/2013
• Published: 01/07/2016
• Est. Priority Date: 02/15/2013
• Status: Abandoned Application

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Alistair Robertson, Jeffrey W. Scott
• Inventors: ROBERTSON, Alistair, SCOTT, Jeffrey W.
• Application Number:
  US14/767,297
• Publication Number:
  US 20160004535A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30185 according to one or more bits in the instruction, e.g. prefix, sub-opcode
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A method of operating a multi-thread capable processor system comprising a plurality of processor pipelines is described. The method comprises fetching an instruction comprising an address and selecting an operation mode based on the address of the fetched instruction, the operation mode being selected from at least a lock-step mode and a multi-thread mode. If the operation mode is selected to be the lock-step mode, the method comprises letting at least two processor pipelines of the multi-thread capable processor system execute the instruction in lock-step mode to obtain respective lock-step results, comparing the respective lock-step results against a comparison criterion for determining whether the respective lock-step results match, and, if the respective lock-step results match, determine a matching result from the respective lock-step results, and writing back the matching results.

Claims

1. A method of operating a multi-thread capable processor system comprising a plurality of processor pipelines, the method comprising:

fetching an instruction comprising an address;

selecting an operation mode based on the address of the fetched instruction, wherein the operation mode is selected from at least a lock-step mode and a multi-thread mode; and

if the operation mode is selected to be the lock-step mode;

letting at least two processor pipelines of the multi-thread capable processor system execute the instruction in lock-step mode to obtain respective lock-step results,

comparing the respective lock-step results against a comparison criterion for determining whether the respective lock-step results match, and,

determining a matching result from the respective lock-step results and writing back the matching results, if the respective lock step results match.

2. A method according to claim 1, further comprising:

signalling an error if the respective lock step results do not match.

3. A method according to claim 1, further comprising:

if the operation mode is selected to be the multi-thread mode;

letting a first processor pipeline of the at least two processor pipelines of the multi-thread capable processor system execute the instruction in a first thread of the multithread mode to obtain a first multi-thread result, and

if a different, second processor pipeline of the at least two processor pipelines is executing a second thread, letting the second processor pipeline continue to execute the second thread to obtain a second multi-thread result.

4. A method according to claim 1, further comprising:

selecting the operation mode from at least a lock step mode, a multi-thread mode, and a single-thread mode; and

if the operation mode is the single-thread mode;

letting one processor pipeline of the multi-thread capable processor system execute the instruction in a single-thread mode to obtain a single-thread result, and

writing back the single-thread result.

5. A method according to claim 1, wherein selecting the operation mode based on the address of the fetched instruction comprises:

obtaining one or more selected access attributes from selecting the access attribute associated with the address of the fetched instruction from an attribute table comprising a plurality of table entries, wherein each table entry defines at least one access attribute for a respective address range, and

the access attributes define at least one or more operation modes for operating instructions associated with addresses in the respective address range; and

selecting the operating mode in dependence on the one or more selected access attributes.

6. A method according to claim 5, wherein the at least one access attributes comprises at least one operation mode control bit, and

the selecting of the operation mode based on the instruction comprises determining a value of the at least one operation mode control bit.

7. A method according to claim 6, wherein the at least one operation mode control bit comprises at least one lock-step bit indicating whether the instruction requires a lock-step execution.

8. A method according to claim 6, wherein the at least one operation mode control bit comprises at least one multi-thread bit indicating whether the instruction requires a multi-thread execution.

9. A method according to claim 6, wherein the at least one operation mode control bit comprises at least one LS/MT-bit indicating whether the instruction requires either a lock-step execution or a multi-thread execution.

10. A method according to claim 6, wherein the at least one operation mode control bit comprises at least one single-thread bit indicating whether the instruction allows a single-thread execution.

11. A method according to claim 5, wherein the at least one operation mode control bit comprises at least one at least one mode-change bit indicating whether the instruction requires a change of operation mode.

12. A method according to claim 1, wherein the at least two processor pipelines of the multi-thread capable processor system are arranged to execute a sequence of instructions using at least a first thread in any operation mode, and to execute instructions in one or more of a lock-step mode or in multi-thread mode using the first thread and at least a second thread.

13. A method according to claim 12, wherein the at least two processor pipelines comprise a master processor pipeline, the master processor pipeline being arranged to execute the first thread.

14. A method according to claim 1, where the selection of the operation mode results in a change of the operation mode from the multithread mode to the lock-step mode, the method further comprising:

halting at least one processor pipeline of the multi-thread capable processor system for making the at least one processor pipeline available for executing the instruction in the lock-step mode;

saving a context of the at least one pipelines that are halted; and

letting the at least one processor pipeline that is halted execute the instruction in lock-step mode together with one or more other pipelines to obtain the respective lock-step results.

15. A method according to claim 1, where the selection of the operation mode results in a change of the operation mode from the multithread mode to the lock-step mode, the method further comprising:

halting at least one processor pipeline of the multi-thread capable processor system for making the at least one processor pipeline available for executing the instruction in the lock-step mode, and

before halting the at least one processor pipeline, letting the at least one processor pipeline complete instructions that are in progress.

16-20. -20. (canceled)