CACHING SYSTEMS AND METHODS WITH SIMULATED NVDRAM

• US 20160004653A1
• Filed: 07/03/2014
• Published: 01/07/2016
• Est. Priority Date: 07/03/2014
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Purkayastha, Saugata Das, Sampathkumar, Kishore Kaniyar
• Granted Patent: US 9,747,228 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4221 being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
• CPC Class Codes: G06F 2212/1041 Resource optimization
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/214 Solid state disk

Abstract

Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD for cache operations. The DRAM and the SSD are sectioned into pages and mapped to pages of the host memory. The SSD is further sectioned into regions comprising one or more pages of the SSD. The HBA is operable to load a page of data from the SSD into a page of the DRAM when directed by a host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of the region of the page of other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.

Claims

1. A system, comprising:

a host processor;

a host memory communicatively coupled to the host processor and sectioned into pages;

a host bus adapter (HBA) communicatively coupled to the host processor and comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD) for cache operations and

an HBA driver operable on the host processor,

wherein the DRAM is sectioned into pages mapped to pages of the host memory and the SSD is sectioned into pages mapped to pages of the DRAM,

wherein the SSD is further sectioned into regions comprising one or more pages of the SSD, and

wherein the HBA driver is operable to load a page of data from the SSD into a page of the DRAM when directed by the host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of a region of the page of the other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority.

2. The system of claim 1, further comprising:

a storage device comprising an operating system executable by the host processor, wherein the operating system comprises an application that is operable to change priorities of the regions of the SSD.

3. The system of claim 2, wherein:

the storage device comprises a table of the priorities of the regions; and

the HBA driver is further operable to direct the host processor to periodically access the list to automatically determine the priorities of the regions.

4. The system of claim 2, wherein:

the operating system is operable to direct the processor to generate a page fault when an application running on the host processor attempts to load the page of data into the DRAM and determines that the data is not in the DRAM.

5. The system of claim 4, wherein:

the page fault directs the HBA driver to determine that the priority of the page being attempted for loading into the DRAM comprises data in a region that is higher than the page of data currently occupying the DRAM; and

in response to determining that the priority is higher, the HBA driver writes the page of data currently occupying the DRAM to the SSD.

6. The system of claim 4, wherein:

the page fault directs the HBA driver to determine that the priority of the page being attempted for loading into the DRAM comprises data in a region that is lower than the page of data currently occupying the DRAM; and

in response to determining that the priority is lower, the HBA driver determines a priority of a next physical region and loads the page being attempted for loading into the DRAM into a page of the next physical region.

7. The system of claim 1, wherein:

the SSD maintains data of the DRAM during a power outage.

8. A method operable in a host system comprising a host processor, a host memory, a host bus adapter (HBA), and an HBA driver, the HBA comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD) for cache operations, the method comprising:

sectioning the host memory into pages;

sectioning the DRAM into pages;

sectioning the SSD into pages and regions, with each region of the SSD comprising one or more pages of the SSD;

mapping the host memory pages to the DRAM pages;

mapping the pages of the DRAM to the pages of the SSD to provide the host processor with direct access to the pages of the SSD through the DRAM;

loading a page of data from the SSD into a page of the DRAM when directed by the host processor;

determining that the page of the DRAM is occupied with other data;

determining a priority of the region of the page of other data occupying the page of the DRAM; and

flushing the other data from the DRAM to the SSD based on the determined priority.

9. The method of claim 8, further comprising:

changing priorities of the regions of the SSD via an application of an operating system directing the host processor.

10. The method of claim 9, further comprising:

maintaining a table of the priorities of the regions; and

periodically accessing the list to automatically determine the priorities of the regions.

11. The method of claim 9, further comprising:

generating a page fault when an application running on the host processor attempts to load the page of data into the DRAM and determines that the data is not in the DRAM.

12. The method of claim 11, further comprising:

in response to generating the page fault, determining that the priority of the page being attempted for loading into the DRAM comprises data in a region that is higher than the page of data currently occupying the DRAM; and

in response to determining that the priority is higher, writing the page of data currently occupying the DRAM to the SSD.

13. The method of claim 11, further comprising:

in response to generating the page fault, determining that the priority of the page being attempted for loading into the DRAM comprises data in a region that is lower than the page of data currently occupying the DRAM;

in response to determining that the priority is lower, determining a priority of a next physical region; and

loading the page being attempted for loading into the DRAM into a page of the next physical region.

14. The method of claim 8, further comprising:

maintaining data of the DRAM in the SSD during a power outage.

15. A non-transitory computer readable medium comprising instructions that, when directed by a processor in a host system comprising a host memory, a host bus adapter (HBA), and an HBA driver, the HBA comprising a Dynamic Random Access Memory (DRAM) and a Solid State Memory (SSD) for cache operations, direct the processor to:

section the host memory into pages;

section the DRAM into pages;

section the SSD into pages and regions, with each region of the SSD comprising one or more pages of the SSD;

map the host memory pages to the DRAM pages;

map the pages of the DRAM to the pages of the SSD to provide the host processor with direct access to the pages of the SSD through the DRAM;

load a page of data from the SSD into a page of the DRAM when directed by the host processor;

determine that the page of the DRAM is occupied with other data;

determine a priority of the region of the page of other data occupying the page of the DRAM; and

flush the other data from the DRAM to the SSD based on the determined priority.

16. The computer readable medium of claim 15, further comprising instructions that direct the processor to:

change priorities of the regions of the SSD via an application of an operating system.

17. The computer readable medium of claim 16, further comprising instructions that direct the processor to:

maintain a table of the priorities of the regions; and

periodically access the list to automatically determine the priorities of the regions.

18. The computer readable medium of claim 16, further comprising instructions that direct the processor to:

generate a page fault when application running on the host processor attempts to load the page of data into the DRAM and determines that the data is not in the DRAM.

19. The computer readable medium of claim 18, further comprising instructions that direct the processor to:

in response to generating the page fault, determine that the priority of the page being attempted for loading into the DRAM comprises data in a region that is higher than the page of data currently occupying the DRAM; and

in response to determining that the priority is higher, right the page of data currently occupying the DRAM to the SSD.

20. The computer readable medium of claim 18, further comprising instructions that direct the processor to:

in response to generating the page fault, determine that the priority of the page being attempted for loading into the DRAM comprises data in a region that is lower than the page of data currently occupying the DRAM;

in response to determining that the priority is lower, determine a priority of a next physical region; and

load the page being attempted for loading into the DRAM into a page of the next physical region.