Fin Spacer Protected Source and Drain Regions in FinFETs

• US 20160005656A1
• Filed: 09/11/2015
• Published: 01/07/2016
• Est. Priority Date: 01/14/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ching, Kuo-Cheng, Hsu, Ting-Hung, Wang, Chao-Hsiung, Liu, Chi-Wen
• Granted Patent: US 9,935,011 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 : with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

Claims

1. A method comprising:

etching a semiconductor substrate to form a first plurality of recesses;

filling the first plurality of recesses to form Shallow Trench Isolation (STI) regions, wherein a portion of the semiconductor substrate between the STI regions forms a semiconductor strip, wherein edges of the semiconductor strip contact sidewalls of the STI regions;

replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is formed over the first semiconductor layer, wherein the first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer;

recessing the STI regions, wherein a portion of the semiconductor strip with edges exposed by the recessed STI regions forms a semiconductor fin;

forming a gate stack over a middle portion of the semiconductor fin;

forming gate spacers on sidewalls of the gate stack;

forming fin spacers on sidewalls of an end portion of the semiconductor fin;

recessing the end portion of the semiconductor fin; and

growing an epitaxial region over the end portion of the semiconductor fin that is recessed.

2. The method of claim 1, wherein the replacing the top portion of the semiconductor strip further comprises:

removing a top portion of the semiconductor strip to form a second recess;

epitaxially growing a first semiconductor layer in the second recess, the first semiconductor layer comprising germanium; and

epitaxially growing a second semiconductor layer in the second recess and over the first semiconductor layer, the second semiconductor layer being substantially free of germanium.

3. The method of claim 1, wherein the forming the gate spacers and the forming the fin spacers comprise:

blanket depositing a spacer layer over the gate stack and the semiconductor fin; and

patterning the spacer layer to form the gate spacers and the fin spacers.

4. The method of claim 3, wherein the patterning the spacer layer comprises:

anisotropically etching the spacer.

5. The method of claim 1, wherein the fin spacers have top ends that are below a top surface of the semiconductor fin and above a top surface of the first semiconductor layer.

6. The method of claim 1, wherein the forming the gate spacers and the forming the fin spacers comprise depositing a silicon nitride layer, and patterning the silicon nitride layer.

7. The method of claim 1, wherein the step of recessing the end portion of the semiconductor fin includes recessing a top portion of the second semiconductor layer, whereas the first semiconductor layer and a bottom portion of the second semiconductor layer are not recessed.

8. The method of claim 1, wherein the step of recessing the end portion of the semiconductor fin forms a third recess over a remaining end portion of the semiconductor fin, wherein the growing the epitaxial region comprises growing the epitaxial region vertically first to fill the third recess before growing the epitaxial region horizontally.

9. The method of claim 1, wherein the growing the epitaxial region comprises in-situ doping an n-type impurity in the epitaxial region.

10. The method of claim 1, further comprising:

forming an Inter-Layer Dielectric (ILD) over the epitaxial region and the fin spacers;

removing the gate stack to form a fourth recess in the ILD, the fourth recess exposing the first and the second semiconductor layers in the middle portion of the semiconductor fin;

after the removing the gate stack, performing an oxidation process on an outer portion of the first semiconductor layer, an inner portion of the first semiconductor layer is not oxidized; and

forming a replacement gate in the recess that is in the ILD.

11. A method of forming a Fin Field-Effect Transistor (FinFET) device, the method comprising:

forming a first and a second semiconductor fin over a substrate, the first and second semiconductor fins being parallel to each other;

forming Shallow Trench Isolation (STI) regions surrounding the first and the second semiconductor fins, wherein top portions of the first and the second semiconductor fins comprise a first epitaxial layer and a second epitaxial layer, with the first epitaxial layer underlying the second epitaxial layer and having a first germanium percentage;

forming a gate stack over respective middle portions of the first and the second semiconductor fins;

forming a fin spacer between end portions of the first and the second semiconductor fins, wherein the end portions of the first and the second semiconductor fins are disposed on a same side of the gate stack, wherein the fin spacer extends continuously on a first sidewall of the first semiconductor fin, a top surface of the STI regions, and a second sidewall of the second semiconductor fin, and wherein an edge of the fin spacer on the first sidewall has a first height larger than a second height of the fin spacer measured at a point midway between the first and the second semiconductor fins;

removing top portions of the second epitaxial layer from the respective end portions of first and the second semiconductor fins; and

epitaxially growing a first source/drain region and a second source/drain region over remaining portions of the second epitaxial layer of the end portions of the first and the second semiconductor fins, respectively.

12. The method of claim 11, wherein the second epitaxial layer is substantially free of germanium.

13. The method of claim 11, further comprising:

forming a gate spacer on a sidewall of the gate stack, wherein the gate spacer and the fin spacer are formed using a same material and are connected.

14. The method of claim 13, wherein forming the gate spacer and the forming the fin spacer comprise:

forming a conformal spacer layer over the gate stack, the STI regions, and the first and the second semiconductor fins; and

patterning the spacer layer to form the gate spacer and the fin spacer.

15. The method of claim 11, wherein the removing the top portions of the second epitaxial layer forms recesses in the end portions of the first and the second semiconductor fins, wherein in the epitaxially growing the first source/drain region and the second source/drain region, the first and the second source/drain regions grow vertically first to fill the recesses, before growing laterally beyond the recesses.

16. The method of claim 11, further comprising:

forming an Inter-Layer Dielectric (ILD) over the gate stack, the first and the second semiconductor fins, and the STI regions;

removing the gate stack to form a recess in the ILD, the recess exposing the first and the second epitaxial layers in the middle portions of the first and the second semiconductor fins;

performing an oxidation process on exposed outer portions of the first and the second epitaxial layers without oxidizing inner portions of the first and the second epitaxial layers; and

forming a replacement gate in the recess of the ILD.

17. The method of claim 16, wherein performing the oxidization process increases a volume of the first epitaxial layer to achieve a desired degree of channel strain.

18. The method of claim 16, wherein performing the oxidization process forms a semiconductor region in the inner portions of the first epitaxial layer, wherein the semiconductor region has a second germanium percentage higher than the first germanium percentage.

19. A method of forming a Fin Field-Effect Transistor (FinFET) device, the method comprising:

forming a first and a second semiconductor fin over a substrate, with Shallow Trench Isolation (STI) regions surrounding the first and the second semiconductor fins, wherein top portions of the first and the second semiconductor fins comprise a germanium-containing first semiconductor layer and a substantially germanium-free second semiconductor layer, with the first semiconductor layer underlying the second semiconductor layer;

forming a gate stack over middle portions of the first and the second semiconductor fins;

forming fin spacers on sidewalls of end portions of the first and the second semiconductor fins, wherein top ends of the fins spacers extend above a top surface of the first semiconductor layer;

removing top portions of the second semiconductor layer, and subsequently, epitaxially growing source/drain regions over the end portions of the first and the second semiconductor fins;

removing the gate stack to expose the first and the second semiconductor layers in the middle portions of the first and the second semiconductor fins; and

oxidizing outer portions of the first semiconductor layer.

20. The method of claim 19, wherein the oxidizing the outer portions of the first semiconductor layer forms a semiconductor oxide region in the outer portions of the first semiconductor layer, and a semiconductor region in inner portions of the first semiconductor layer, wherein the semiconductor oxide region has a first portion overlying the semiconductor region and a second portion underlying the semiconductor region.