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Fin Spacer Protected Source and Drain Regions in FinFETs

  • US 20160005656A1
  • Filed: 09/11/2015
  • Published: 01/07/2016
  • Est. Priority Date: 01/14/2013
  • Status: Active Grant
First Claim
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1. A method comprising:

  • etching a semiconductor substrate to form a first plurality of recesses;

    filling the first plurality of recesses to form Shallow Trench Isolation (STI) regions, wherein a portion of the semiconductor substrate between the STI regions forms a semiconductor strip, wherein edges of the semiconductor strip contact sidewalls of the STI regions;

    replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer, wherein the second semiconductor layer is formed over the first semiconductor layer, wherein the first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer;

    recessing the STI regions, wherein a portion of the semiconductor strip with edges exposed by the recessed STI regions forms a semiconductor fin;

    forming a gate stack over a middle portion of the semiconductor fin;

    forming gate spacers on sidewalls of the gate stack;

    forming fin spacers on sidewalls of an end portion of the semiconductor fin;

    recessing the end portion of the semiconductor fin; and

    growing an epitaxial region over the end portion of the semiconductor fin that is recessed.

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