Semiconductor Device Having Electrically Floating Body Transistor, Semiconductor Device Having Both Volatile and Non-Volatile Functionality and Method of Operating
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Abstract
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
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Citations
236 Claims
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1-199. -199. (canceled)
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200. A single polysilicon floating gate semiconductor memory cell comprising:
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a substrate; a floating body region exposed at a surface of said substrate and configured to store volatile memory; a single polysilicon floating gate configured to store nonvolatile data; an insulating region insulating said floating body region from said single polysilicon floating gate; and first and second regions exposed at said surface at locations other than where said floating body region is exposed; wherein said floating gate is configured to receive transfer of data stored by the volatile memory. - View Dependent Claims (201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211)
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212-219. -219. (canceled)
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220. A single polysilicon floating gate semiconductor memory cell comprising:
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a substrate; a floating body region for storing data as volatile memory, and a single polysilicon floating gate for storing data as non-volatile memory; wherein said floating body region stores the data stored as volatile memory independently of said data stored as non-volatile memory, and said single polysilicon floating gate stores said data stored as non-volatile memory independently of said data stored as volatile memory. - View Dependent Claims (221, 222, 223, 224, 234, 236)
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225-233. -233. (canceled)
Specification