APPARATUS AND SYSTEM FOR DIGITALLY CONTROLLED OSCILLATOR

• US 20160006443A1
• Filed: 08/20/2015
• Published: 01/07/2016
• Est. Priority Date: 03/22/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: KURD, Nasser A., ABDELMONEUM, Mohamed A., LOTFY, Amr M., ABDELSALAM, Mohamed A., EL MAHALAWY, Mohammed W.
• Granted Patent: US 10,707,878 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03L 7/00 Automatic control of frequency or phase; Synchronisation
• CPC Class Codes: H03L 7/0818 the controlled phase shifter comprising coarse and fine delay or phase-shifting means
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider

Abstract

Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.

Claims

1-23. -23. (canceled)

24. An apparatus comprising:

a digitally controlled oscillator (DCO);

a supply node to provide a regulated power supply to the DCO through a variable resistor; and

a digital loop filter (DLF) coupled to the DCO to generate a digital code according to a phase error, wherein the digital code is to adjust resistance of the variable resistor to modify the regulated power supply.

25. The apparatus of claim 24 comprises a circuit to receive the digital code and to generate a control signal according to the digital code.

26. The apparatus of claim 24 comprises a phase detector to detect the phase error between a reference signal and a feedback signal.

27. The apparatus of claim 26, wherein the phase detector is to provide the phase error indicating a phase lead condition or a phase lag condition.

28. The apparatus of claim 26 comprises a divider to receive an output of the DCO and to provide the feedback signal.

29. The apparatus of claim 24, wherein the DCO comprises an odd number of delay cells.

30. The apparatus of claim 29, wherein at least one of the delay cells is an inverter.

31. The apparatus of claim 24, wherein the DCO comprises an even number of delay cells.

32. The apparatus of claim 31, wherein at least one of the delay cells is an inverter.

33. The apparatus of claim 24, wherein the DCO comprises delay cells coupled together in a cyclic manner.

34. The apparatus of claim 24, wherein at least one circuit coupled to the DCO receives a power supply separate from the regulated power supply.

35. An apparatus comprising:

a digitally controlled oscillator (DCO);

a supply node to provide a regulated power supply to the DCO through a variable resistor; and

a digital loop filter (DLF) coupled to the DCO to generate a digital code according to a phase error, wherein the variable resistor has a resistance which is adjustable according to the digital code to modify the regulated power supply.

36. The apparatus of claim 35 comprises a circuit to receive the digital code and to generate a control signal according to the digital code.

37. The apparatus of claim 35, wherein at least one circuit coupled to the DCO receives a power supply separate from the regulated power supply.

38. An apparatus comprising:

an input supply node;

an output supply node;

a variable resistor coupled to the input supply node and to the output supply node; and

a digital phase locked loop (PLL) including;

a phase detector to detect a phase error between a reference signal and a feedback signal;

a digital loop filter (DLF) to generate a digital code according to the phase error; and

a digitally controlled oscillator (DCO) coupled to the output supply node, wherein the digital code is to adjust resistance of the variable resistor to modify an output supply provided by the output supply node.

39. The apparatus of claim 38 comprises a circuit to receive the digital code and to generate a control signal according to the digital code.

40. The apparatus of claim 38 comprises a phase detector to detect the phase error between a reference signal and a feedback signal.

41. The apparatus of claim 40, wherein the phase detector is to provide the phase error indicating a phase lead condition or a phase lag condition.

42. An apparatus comprising:

a digital loop filter (DLF) to generate a digital code according to a phase error;

an input supply node;

an output supply node;

a variable resistor coupled to the input supply node and to the output supply node; and

a digitally controlled oscillator (DCO) coupled to the output supply node, wherein the digital code is to adjust resistance of the variable resistor to modify an output supply provided by the output supply node.

43. The apparatus of claim 42 comprises a circuit to receive the digital code and to generate a control signal according to the digital code.

44. The apparatus of claim 42 comprises a phase detector to detect the phase error between a reference signal and a feedback signal.

45. The apparatus of claim 44, wherein the phase detector is to provide the phase error indicating a phase lead condition or a phase lag condition.

46. The apparatus of claim 44 comprises a divider to receive an output of the DCO and to provide the feedback signal.

47. The apparatus of claim 42, wherein the output supply is a regulated supply.

48. A system comprising:

a memory;

a processor coupled to the memory, the processor comprising;

a digitally controlled oscillator (DCO);

a supply node to provide a regulated power supply to the DCO through a variable resistor; and

a digital loop filter (DLF) coupled to the DCO to generate a digital code according to a phase error, wherein the digital code is to adjust resistance of the variable resistor to modify the regulated power supply; and

a wireless interface for allowing the processor to couple to another device.

49. The system of claim 48, wherein processor comprises a circuit to receive the digital code and to generate a control signal according to the digital code.

50. A method comprising:

providing a regulated power supply to a digitally controlled oscillator (DCO) through a variable resistor; and

generating a digital code according to a phase error, wherein the variable resistor has a resistance which is adjustable according to the digital code to modify the regulated power supply.

51. The method of claim 50 comprises:

receiving the digital code and generating a control signal according to the digital code.

52. The method of claim 50 detecting the phase error between a reference signal and a feedback signal.