MICROFABRICATED ULTRASONIC TRANSDUCERS AND RELATED APPARATUS AND METHODS

• US 20160009544A1
• Filed: 07/14/2015
• Published: 01/14/2016
• Est. Priority Date: 03/02/2015
• Status: Abandoned Application

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Alie, Susan A., Fife, Keith G., Sanchez, Nevada J., Ralston, Tyler S.
• Application Number:
  US14/799,484
• Publication Number:
  US 20160009544A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 3/0021 Transducers for transforming electrical into mechanical energy or vice versa dynamo-electric machines H02K99/00; electrostatic machines H02N1/00; piezoelectric devices H10N30/00
• CPC Class Codes: B81B 7/04 Networks or arrays of similar microstructural devices
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: B81C 1/00357 involving bonding one or several substrates on a non-temporary support, e.g. another substrate
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/29144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83005 : being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/83203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/83805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

Micromachined ultrasonic transducers integrated with complementary metal oxide semiconductor (CMOS) substrates are described, as well as methods of fabricating such devices. Fabrication may involve two separate wafer bonding steps. Wafer bonding may be used to fabricate sealed cavities in a substrate. Wafer bonding may also be used to bond the substrate to another substrate, such as a CMOS wafer. At least the second wafer bonding may be performed at a low temperature.

Claims

1. A method of bonding an engineered substrate having first and second wafers bonded together, the first wafer having an isolation trench isolating an electrode region of the first wafer, the method comprising:

forming a redistribution layer on an integrated circuit (IC) wafer having an IC;

forming a solder bump array on the redistribution layer; and

solder bump bonding the engineered substrate with the IC wafer such that the first wafer of the engineered substrate is between the IC wafer and the second wafer of the engineered substrate,

wherein a first solder bump of the solder bump array electrically contacts the electrode region of the first wafer.

2. The method of claim 1, wherein the first wafer includes a first side proximate the second wafer and a second side distal the second wafer, and wherein the method further comprises, prior to solder bump bonding the engineered substrate with the IC wafer, forming a redistribution layer on the second side of the first wafer.

3. The method of claim 1, wherein the engineered substrate comprises a plurality of cavities in the first wafer or second wafer, wherein a first cavity of the plurality of cavities is aligned with the electrode region.

4. The method of claim 1, wherein solder bump bonding the engineered substrate with the IC wafer is performed in a wafer-scale packaging foundry.

5. The method of claim 1, further comprising dicing the engineered substrate and IC wafer subsequent to solder bump bonding the engineered substrate with the IC wafer.

6. The method of claim 1, wherein the first wafer of the engineered substrate has a thickness between approximately 200 microns and approximately 500 microns, and wherein the first wafer is not thinned prior to the solder bump bonding.

7. The method of claim 1, wherein the first wafer of the engineered substrate has a thickness between approximately 5 microns and approximately 200 microns.

8. The method of claim 1, further comprising electrically coupling the IC to the second wafer of the engineered substrate.

9. An apparatus, comprising:

an engineered substrate including first and second substrates bonded together, wherein the first substrate has an isolation trench defining an electrode region;

an integrated circuit (IC) substrate, having an IC, bonded with the first substrate of the engineered substrate and including a redistribution layer; and

a solder bump array on the redistribution layer and forming a solder bump bond between the first substrate and the IC substrate,

wherein a first solder bump of the solder bump array electrically contacts the electrode region.

10. The apparatus of claim 9, wherein the first substrate includes a first side proximate the second substrate and a second side distal the second substrate, and wherein the apparatus further comprises a redistribution layer on the second side of the first substrate.

11. The apparatus of claim 9, wherein the engineered substrate comprises a plurality of sealed cavities.

12. The apparatus of claim 11, wherein a first cavity of the plurality of cavities is aligned with the electrode region.

13. The apparatus of claim 9, wherein the first substrate of the engineered substrate has a thickness between approximate 200 microns and approximately 500 microns.

14. The apparatus of claim 9, wherein the first substrate of the engineered substrate has a thickness between approximately 5 microns and approximately 200 microns.

15. The apparatus of claim 9, further comprising an electrical path coupling the IC to the second substrate of the engineered substrate.