Configurable Per-Task State Counters For Processing Cores In Multi-Tasking Processing Systems

• US 20160011907A1
• Filed: 07/14/2014
• Published: 01/14/2016
• Est. Priority Date: 07/14/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Moyer, William C., Pillar, John F.
• Granted Patent: US 9,785,473 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

Configurable per-task state counters for processing cores in multi-tasking processing systems are disclosed along with related methods. In part, the disclosed embodiments include a work scheduler and a plurality of processing cores. The work scheduler assigns tasks to the processing cores, and the processing cores concurrently process multiple assigned tasks using a plurality of processing states. Further, task state counters are provided for each assigned task, and these task state counters are incremented for each cycle that the task stays within selected processing states to generate per-task state count values for the assigned tasks. These per-task state count values are reported back to the work scheduler when processing for the task ends. The work scheduler can then use one or more of the per-task state count values to adjust how new tasks are assigned to the processing cores.

Claims

1. A method for operating a multi-tasking processing system, comprising:

assigning tasks to a plurality of processing cores for a multi-tasking processing system, each processing core being configured to process multiple assigned tasks using a plurality of processing states; and

at each processing core;

concurrently processing the multiple assigned tasks using the plurality of processing states; and

for each task, counting processing cycles that the task stays within a selected set of the plurality of processing states to generate a per-task state count value for the task.

2. The method of claim 1, wherein at each processing core, the method further comprises reporting the per-task state count values to a work scheduler for the multi-tasking processing system.

3. The method of claim 1, further comprising selecting the set of the plurality of processing states for each processing core.

4. The method of claim 3, further comprising adjusting the set of the plurality of processing states for each processing core based upon at least one of an operational state of the multi-tasking processing system or performance of the multi-tasking processing system.

5. The method of claim 3, wherein the selecting step comprises setting one or more bits within a configuration register for each processing core to select the set of the plurality of processing states.

6. The method of claim 5, further comprising setting one or more bits within the configuration register for each processing core to enable or disable task state counting.

7. The method of claim 1, wherein the plurality of processing states comprise at least one of an unassigned state, a waiting state, an inhibit state, an accelerating state, or an executing state.

8. The method of claim 1, further comprising storing the per-task state count values from the plurality of processing cores in a data storage medium.

9. The method of claim 8, further comprising assigning one or more new tasks to the plurality of processing cores based upon one or more of the stored per-task state count values.

10. The method of claim 1, wherein the counting step for each task comprises incrementing a value within a counter field for a count register for each task being concurrently processed by the processing core.

11. The method of claim 10, further comprising setting one or more bits within the count register to indicate an overflow condition and to disable further counting.

12. A multi-tasking processing system, comprising:

a plurality of processing cores, each processing core being configured to concurrently process multiple tasks using a plurality of processing states; and

a work scheduler processor configured to assign tasks to the plurality of processing cores;

wherein each processing core comprises;

a core task scheduler configured to schedule processing of the multiple tasks within the processing core;

a plurality of task state counters, each task state counter being associated with one of the multiple tasks; and

a task state tracker configured to increment each task state counter for each processing cycle that the task associated with that task state counter stays within a selected set of the plurality of processing states to generate a per-task state count value for each task.

13. The multi-tasking system of claim 12, wherein each processing core is further configured to report the per-task state count values from the task state counters to the work scheduler.

14. The multi-tasking processing system of claim 13, further comprising a data storage medium configured to store the per-task state count values from the plurality of processing cores.

15. The multi-tasking processing system of claim 14, wherein the work scheduler is further configured to assign one or more new tasks to the plurality of processing cores based upon one or more of the stored per-task state count values.

16. The multi-tasking processing system of claim 12, wherein each of the plurality of processing cores is further configured to allow programmable selection of the set of the plurality of processing states.

17. The multi-tasking processing system of claim 16, further comprising a configuration register associated with each core task scheduler, and wherein one or more bits within the configuration register are used to select the set of the plurality of processing states.

18. The multi-tasking processing system of claim 17, wherein one or more bits within the configuration register are used to enable or disable task state counting.

19. The multi-tasking processing system of claim 12, wherein the plurality of task state counters each comprise a count register having a counter field.

20. The multi-tasking processing system of claim 19, wherein one or more bits within each count register are used to indicate an overflow condition and to disable further counting.