Segmentation of Blocks for Faster Bit Line Settling/Recovery in Non-Volatile Memory Devices

• US 20160012903A1
• Filed: 07/10/2014
• Published: 01/14/2016
• Est. Priority Date: 07/10/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Nguyen, Hao, Lee, Seungpil, Mui, Man, Desai, Amul Dhirajbhai
• Granted Patent: US 9,633,742 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.

Claims

1. A non-volatile memory circuit comprising:

an array of non-volatile memory cells formed as a plurality of multi-cell erase blocks;

a plurality of bit lines spanning the plurality of erase blocks to which the memory cells of the blocks are connected; and

sensing circuitry connected to the array, including a plurality of sense amp circuits connected to the bit lines and logic circuitry whereby a timing for a sensing operation of selected memory cells is varied based upon a physical distance along the bit lines from the sense amp circuits to the block that includes the selected memory cells.

2. The non-volatile memory circuit of claim 1, wherein each of the blocks belongs to one of a plurality of block groups, each of the block groups containing one or more adjacent blocks of the array, wherein the blocks of a group use a shared timing for the sensing operation of selected memory cells belonging thereto and the different block groups use different timings for the sensing operation of selected memory cells belonging thereto.

3. The non-volatile memory circuit of claim 2, wherein the shared timings of the different block groups differ from each other by an offset.

6. The non-volatile memory circuit of claim 3, wherein initial values for the offsets are based upon device characterization tests.

7. The non-volatile memory circuit of claim 3, wherein initial values for the offsets are set prior to the memory circuit being supplied to a user.

8. The non-volatile memory circuit of claim 7, wherein one of more of the offsets are changed after the non-volatile memory circuit has aged.

9. The non-volatile memory circuit of claim 1, wherein the different timings vary in a number of clock cycles allotted for a phase of the sensing operation.

10. The non-volatile memory circuit of claim 9, wherein the phase of the sensing operation is a pre-charge operation.

11. The non-volatile memory circuit of claim 1, wherein the sensing operation is a data read.

12. The non-volatile memory circuit of claim 1, wherein the sensing operation is a program verify.

13. The non-volatile memory circuit of claim 1, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

4. (canceled)

5. (canceled)

14. A method comprising:

receiving at a non-volatile memory circuit a command that includes a sensing operation for one or more selected memory cells, the memory circuit including an array of non-volatile memory cells formed as a plurality of multi-cell erase blocks with a plurality of bit lines to which the memory cells of the blocks are connected spanning the plurality of erase blocks and having a plurality of sense amp circuits connected to the bit lines;

determining the erase block to which the selected memory cells belong; and

setting a timing for the sensing operation based upon a physical distance along the bit lines from the determined block to the sense amp circuits.

15. The method of claim 14, wherein the memory circuit configures each of the blocks belongs to one of a plurality of block groups, each of the block groups containing one or more adjacent blocks of the array, wherein the blocks of a group use a shared timing for the sensing operation of selected memory cells belonging thereto and the different groups use different timings for the sensing operation of selected memory cells belonging thereto,

wherein determining the erase block to which the selected memory cells belong comprises determining the block group to which the determined block belongs, and

wherein setting a timing includes selecting the shared timing for the block group to which the determined block belongs.

16. The method of claim 15, wherein the shared timings of different block groups differ from each other by an offset.

17. The method of claim 16, wherein the offsets are settable parameters.

18. The method of claim 16, wherein the offsets differ by a number of clock cycles.

19. The method of claim 14, wherein the non-volatile memory circuit is a monolithic three-dimensional semiconductor memory device where the memory cells are arranged in multiple physical levels above a silicon substrate and comprise a charge storage medium.

20. A non-volatile memory circuit comprising:

an array of non-volatile memory cells formed as a plurality of multi-cell erase blocks;

a bit line spanning the plurality of erase blocks to which the memory cells of the blocks are connected; and

sensing circuitry connected to the array, including a plurality of sense amp circuits connected to the bit line and logic circuitry whereby a timing for a sensing operation of selected memory cells is varied based upon a physical distance along the bit line from the sense amp circuits to the block that includes the selected memory cells.

21. The non-volatile memory circuit of claim 20, wherein each of the blocks belongs to one of a plurality of block groups, each of the block groups containing one or more adjacent blocks of the array, wherein the blocks of a group use a shared timing for the sensing operation of selected memory cells belonging thereto and different block groups use different timings for the sensing operation of selected memory cells belonging thereto.

22. The non-volatile memory circuit of claim 21, wherein the shared timings of the different block groups differ from each other by an offset.