THREE DIMENSIONAL PACKAGE ASSEMBLIES AND METHODS FOR THE PRODUCTION THEREOF

• US 20160013076A1
• Filed: 07/14/2014
• Published: 01/14/2016
• Est. Priority Date: 07/14/2014
• Status: Abandoned Application

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Michael B. Vincent, Zhiwei Gong
• Inventors: VINCENT, MICHAEL B., GONG, ZHIWEI
• Application Number:
  US14/330,971
• Publication Number:
  US 20160013076A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1064 Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/03 : all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1421 : RF devices
• CPC Class Codes: H01L 2924/1434 : Memory

Abstract

Three dimensional (3D) package assembly and methods for producing 3D package assembly are provided. In one embodiment, the method includes positioning a first plurality of microelectronic devices on a pre-singulated substrate package array. The microelectronic devices can be, for example, semiconductor; and the pre-singulated substrate package array can be a molded substrate panel. The first plurality of microelectronic devices is encapsulated while supported by the pre-singulated substrate package array to produce a direct-built panel containing the first plurality of microelectronic devices. The direct-built panel and the pre-singulated substrate package array are then singulated to yield a plurality of 3D package assemblies each comprised of a substrate package and a direct-built package. The direct-built package is bonded to the substrate package and containing at least one of the first plurality of microelectronic devices.

Claims

1. A method for fabricating three dimensional (3D) package assemblies, the method comprising:

positioning a first plurality of microelectronic devices on a pre-singulated substrate package array;

encapsulating the first plurality of microelectronic devices while supported by the pre-singulated substrate package array to produce a direct-built panel containing the first plurality of microelectronic devices; and

singulating the direct-built panel and the pre-singulated substrate package array to yield a plurality of 3D package assemblies each comprised of a substrate package and a direct-built package, the direct-built package bonded to the substrate package and containing at least one of the first plurality of microelectronic devices.

2. The method of claim 1 wherein the first plurality of microelectronic devices comprise semiconductor die, and wherein positioning comprises bonding the semiconductor die in a face-up orientation to the pre-singulated substrate package array.

3. The method of claim 2 wherein the pre-singulated substrate package array comprises a molded panel over which one or more Redistribution Layers (RDLs) are formed, and wherein bonding comprises bonding the semiconductor die to the RDLs.

4. The method of claim 1 wherein the first plurality of microelectronic devices comprise semiconductor die having frontsides, and wherein encapsulating comprises utilizing a film assist molding process to encapsulate the semiconductor die, while preventing the flow of mold material onto the frontsides of the semiconductor die.

5. The method of claim 1 wherein the first plurality of microelectronic devices comprise semiconductor die over which interconnect buffer layers are formed, and wherein encapsulating comprises:

overmolding the semiconductor die such that mold material covers the interconnect buffer layers; and

removing portions of the mold material overlying the interconnect buffer layers to expose the interconnect buffer layers through a frontside surface of the direct-built panel.

6. The method of claim 5 further comprising producing one or more Redistribution Layers (RDLs) over the frontside surface of the direct-built panel, the RDLs containing interconnect lines electrically coupled to the semiconductor die through the interconnect buffer layers.

7. The method of claim 1 wherein the first plurality of microelectronic devices comprise semiconductor die having bond pads, and wherein encapsulating comprises:

dispensing a photoimagable dielectric material around the semiconductor die and over the bond pads; and

photo-imaging the photoimagable dielectric material to create openings therein exposing the bond pads.

8. The method of claim 7 further comprising positioning a pre-mold frame on the pre-singulated substrate package array prior to dispensing the photoimagable dielectric material, the pre-mold frame having openings in which the semiconductor die are received.

9. The method of claim 1 wherein the pre-singulated substrate package array contains a second plurality of microelectronic devices, and wherein positioning comprises placing each of the first plurality of microelectronic devices at a location vertically overlying at least one of the second plurality of microelectronic devices.

10. The method of claim 1 further comprising, for one or more of the plurality of 3D package assemblies, forming side connect traces on at least one sidewall of the 3D package assembly vertically interconnecting the substrate package and the direct-built package.

11. A method for producing three dimensional (3D) package assemblies, the method comprising:

positioning a first microelectronic device on a substrate package containing a second microelectronic device;

fabricating a direct-built Fan-Out Wafer Level Package (FO-WLP) around the first microelectronic device and over the substrate package; and

forming at least one side connect trace extending from a sidewall of the substrate package to an aligning sidewall of the direct-built FO-WLP to interconnect the first and second microelectronic devices.

12. The method of claim 11 wherein positioning comprises bonding the first microelectronic device to the substrate package, while the substrate package is interconnected with a plurality of other substrate packages as a substrate panel.

13. The method of claim 12 wherein the first microelectronic device comprises a semiconductor die, and wherein positioning comprises rotationally aligning the semiconductor die to the substrate panel.

14. The method of claim 12 wherein fabricating comprises:

encapsulating the first microelectronic device along with a plurality of other microelectronic device to produce a direct-built panel bonded to the substrate panel;

producing one or more Redistribution Layers (RDLs) over the direct-built panel; and

singulating the direct-built panel and the substrate panel to yield a plurality of 3D package assemblies.

15. A three dimensional (3D) package assembly, comprising:

a substrate package;

a direct-built package fabricated over the substrate package;

a first microelectronic device contained within the direct-built package;

a second microelectronic device contained within substrate package; and

one or more side connect traces extending from a sidewall of the substrate package to an aligning sidewall of the direct-built package to electrically interconnect the first and second microelectronic devices.

16. The 3D package assembly of claim 15 wherein the direct-built package comprises a Fan-Out Wafer Level Package.

17. The 3D package assembly of claim 15 further comprising an adhesive layer bonding the first microelectronic device to the substrate package.

18. The 3D package assembly of claim 17 wherein the substrate package comprises one or more Redistribution Layers (RDLs), and wherein the first microelectronic device comprises a semiconductor die having a backside bonded to the RDLs.

19. The 3D package assembly of claim 15 wherein the first microelectronic device comprises a semiconductor die, and wherein the direct-built package comprises a molded body having a thickness substantially equivalent to the height of the semiconductor die.

20. The 3D package assembly of claim 15 wherein the first and second microelectronic devices overlap, as taken along a vertical axis extending through the 3D package assembly.