METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

• US 20160013104A1
• Filed: 08/10/2014
• Published: 01/14/2016
• Est. Priority Date: 07/08/2014
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Hung, Ching-Wen, Wu, Jia-Rong, Chang, Tsung-Hung, Lin, Ching-Ling, Huang, Chih-Sen, Chen, Yi-Wei, Lin, Chun-Hsien, Lee, Yi-Hui
• Granted Patent: US 9,324,610 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, a contact etch stop layer (CESL) around the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate;

removing part of the ILD layer to form a plurality of contact holes exposing the source/drain region and the CESL;

forming a first metal layer and a second metal layer in the contact holes, wherein the first metal layer contacts the CESL directly;

performing a first thermal treatment process after forming the first metal layer and the second metal layer; and

performing a second thermal treatment process.

2. The method of claim 1, further comprising:

forming a fin-shaped structure on the substrate; and

forming the at least one metal gate on the fin-shaped structure.

3. The method of claim 1, wherein the first thermal treatment process comprises a soak anneal process, and the second thermal treatment process comprises a spike anneal process.

4. The method of claim 1, wherein the temperature of the first thermal treatment process is between 500°

C. to 600°

C.

5. The method of claim 1, wherein the temperature of the second thermal treatment process is between 600°

C. to 950°

C.

6. The method of claim 1, wherein the duration of the first thermal treatment process is between 10 seconds to 60 seconds.

7. The method of claim 1, wherein the duration of the second thermal treatment process is between 100 milliseconds to 5 seconds.

8. The method of claim 1, further comprising forming a second metal layer after forming the first metal layer.

9. The method of claim 8, wherein the first metal layer is selected from the group consisting of Ti, Co, Ni, and Pt, and the second metal layer comprises TiN.

10. The method of claim 8, further comprising:

forming an epitaxial layer on the source/drain region;

forming a dielectric layer on the ILD layer;

forming the contact holes in the dielectric layer and the ILD layer;

forming the first metal layer and the second metal layer in the contact holes;

performing the first thermal treatment process and the second thermal treatment process for forming a silicide on the epitaxial layer;

forming a third metal layer to fill the contact holes; and

performing a planarizing process to partially remove the third metal layer, the second metal layer, and the first metal layer.

11. The method of claim 10, wherein the third metal layer comprises tungsten.

12. The method of claim 10, wherein the silicide comprises a C54 phase structure.

13. The method of claim 1, further comprising performing a pre-clean process before forming the first metal layer.

14. A semiconductor device, comprising:

a substrate;

a metal gate on the substrate;

a contact etch stop layer (CESL) around the metal gate;

a source/drain region adjacent to the metal gate in the substrate;

an interlayer dielectric (ILD) layer on the substrate and around the metal gate;

a plurality of contact plugs electrically connected to the source/drain region and the metal gate, wherein each of the contact plugs comprises a first metal layer surrounding a second metal layer and a third metal layer; and

a silicide between the contact plugs and the source/drain region, wherein the silicide comprises a C54 phase structure and the CESL, the first metal layer, the second metal layer, and the third metal layer are all disposed on the silicide.

15. The semiconductor device of claim 14, further comprising a fin-shaped structure between the substrate and the metal gate.

16. The semiconductor device of claim 14, further comprising an epitaxial layer between the silicide and the source/drain region.

18. The semiconductor device of claim 14, wherein the second metal layer directly contacts the silicide.

19. The semiconductor device of claim 14, wherein the first metal layer is selected from the group consisting of Ti, Co, Ni, and Pt, the second metal layer comprises TiN, and the third metal layer comprises W.

17. (canceled)