METHOD TO IMPROVE MEMORY CELL ERASURE
First Claim
1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:
- a semiconductor substrate including a first source/drain region and a second source/drain region;
an erase gate located over the first source/drain region; and
a floating gate and a word line located over the semiconductor substrate between the first and second source/drain regions, wherein the floating gate is arranged between the word line and the erase gate, and wherein the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate.
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Abstract
A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.
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Citations
20 Claims
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1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:
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a semiconductor substrate including a first source/drain region and a second source/drain region; an erase gate located over the first source/drain region; and a floating gate and a word line located over the semiconductor substrate between the first and second source/drain regions, wherein the floating gate is arranged between the word line and the erase gate, and wherein the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of manufacturing a semiconductor structure of a split gate flash memory cell, said method comprising:
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receiving a semiconductor substrate; forming over the semiconductor substrate a floating gate including a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on first opposing sides, respectively, of the floating gate; and forming a word line and an erase gate on second opposing sides of the floating gate. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A semiconductor structure of split gate flash memory cells, said semiconductor structure comprising:
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a semiconductor substrate including a first pair of source/drain regions, a second pair of source/drain regions, and an isolation region arranged between the first and second pairs of source/drain regions; a first erase gate located over a source/drain region of the first pair; a first word line and a first floating gate located over the semiconductor substrate between the source/drain regions of the first pair, wherein the first floating gate is arranged between the first word line and the first erase gate, and wherein the first floating gate includes a pair of protrusions extending vertically up from a top surface of the first floating gate and arranged on opposing sides, respectively, of the first floating gate; a second erase gate located over a source/drain region of the second pair; and a second word line and a second floating gate located over the semiconductor substrate between the source/drain regions of the second pair, wherein the second floating gate is arranged between the second word line and the second erase gate, and wherein the second floating gate includes a pair of protrusions extending vertically up from a top surface of the second floating gate and arranged on opposing sides, respectively, of the second floating gate; wherein one of the opposing sides of each floating gate faces the isolation region.
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Specification