METHOD TO IMPROVE MEMORY CELL ERASURE

• US 20160013195A1
• Filed: 07/09/2014
• Published: 01/14/2016
• Est. Priority Date: 07/09/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsao, Tsun-Kai, Tsair, Yong-Shiuan, Shih, Hung-Ling, Liu, Po-Wei, Huang, Wen-Tuo
• Granted Patent: US 9,287,280 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.

Claims

1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:

a semiconductor substrate including a first source/drain region and a second source/drain region;

an erase gate located over the first source/drain region; and

a floating gate and a word line located over the semiconductor substrate between the first and second source/drain regions, wherein the floating gate is arranged between the word line and the erase gate, and wherein the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate.

2. The semiconductor structure according to claim 1, wherein the pair of protrusions extend vertically up about 20-180 Angstroms (A) from a planar interface between the protrusions and a base region of the floating gate.

3. The semiconductor substrate according to claim 1, wherein each protrusion extends between the word line and the erase gate.

4. The semiconductor structure according to claim 1, wherein the floating gate includes a base region and a protrusion region atop the base region, the protrusion region including the protrusions, and the base region having the profile of an isosceles trapezoid increasing in width towards the semiconductor structure.

5. The semiconductor structure according to claim 1, wherein each protrusion culminates in a point or tip on a corresponding one of the opposing sides.

6. The semiconductor structure according to claim 5, wherein the protrusions each include a sidewall arcing gradually with increasing slope to the point or tip.

7. The semiconductor structure according to claim 5, wherein the protrusions each include a sidewall intersecting the point or tip and running coplanar with a sidewall of a base region of the floating gate, the protrusion extending from a top surface of the base region.

8. The semiconductor structure according to claim 1, further including:

a control gate arranged over the floating gate; and

an inter-gate dielectric region arranged between the control gate and the floating gate, the inter-gate dielectric region conformally lining the protrusions.

9. The semiconductor structure according to claim 1, wherein the semiconductor substrate further includes a third source/drain region, wherein the second source/drain region is arranged between the first and third source/drain regions, and wherein the semiconductor structure further includes:

a second floating gate and a second word line located over the semiconductor substrate between the second and third source/drain regions, wherein the second floating gate is arranged between the second word line and the erase gate, and wherein the second floating gate includes a pair of protrusions extending vertically up from a top surface of the second floating gate and arranged on opposing sides, respectively, of the second floating gate.

10. A method of manufacturing a semiconductor structure of a split gate flash memory cell, said method comprising:

receiving a semiconductor substrate;

forming over the semiconductor substrate a floating gate including a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on first opposing sides, respectively, of the floating gate; and

forming a word line and an erase gate on second opposing sides of the floating gate.

11. The method according to claim 10, further including:

forming the floating gate using a dry etch with an etch recipe comprising primarily hydrogen bromide (HBr) and oxygen.

12. The method according to claim 10, forming the protrusions to each extend between the second opposing sides.

13. The method according to claim 10, further including:

receiving a semiconductor structure having a first conductive layer embedded within a top, planar surface of a first dielectric layer arranged over the semiconductor substrate;

forming a recess in the first conductive layer by performing a first, dry etch of the semiconductor structure using an etch recipe that preferentially removes the first conductive layer while leaving the first dielectric layer; and

forming the pair of protrusions by recessing the first dielectric layer relative to the remaining first conductive layer.

14. The method according to claim 13, further including:

forming the recess with a depth of about 20-180 Angstroms (A).

15. The method according to claim 13, further including:

forming the recess with a dry etch recipe comprising primarily hydrogen bromide (HBr) and oxygen.

16. The method according to claim 15, further including:

forming the recess by diluting the etch recipe with helium (He) and argon (Ar) gases.

17. The method according to claim 13, further including:

forming the recess to arc between the first opposing sides.

18. The method according to claim 13, further including:

forming a second dielectric layer conformally lining the remaining first conductive layer, including the protrusions;

forming a second conductive layer over the second dielectric layer; and

forming a control gate by performing a second etch through the second conductive layer, the second dielectric layer, and partially into the first conductive layer.

19. The method according to claim 18, further including:

forming spacers on opposing sides of the control gate corresponding to the second opposing sides; and

forming the floating gate by performing a third etch through exposed portions of the remaining first conductive layer.

20. A semiconductor structure of split gate flash memory cells, said semiconductor structure comprising:

a semiconductor substrate including a first pair of source/drain regions, a second pair of source/drain regions, and an isolation region arranged between the first and second pairs of source/drain regions;

a first erase gate located over a source/drain region of the first pair;

a first word line and a first floating gate located over the semiconductor substrate between the source/drain regions of the first pair, wherein the first floating gate is arranged between the first word line and the first erase gate, and wherein the first floating gate includes a pair of protrusions extending vertically up from a top surface of the first floating gate and arranged on opposing sides, respectively, of the first floating gate;

a second erase gate located over a source/drain region of the second pair; and

a second word line and a second floating gate located over the semiconductor substrate between the source/drain regions of the second pair, wherein the second floating gate is arranged between the second word line and the second erase gate, and wherein the second floating gate includes a pair of protrusions extending vertically up from a top surface of the second floating gate and arranged on opposing sides, respectively, of the second floating gate;

wherein one of the opposing sides of each floating gate faces the isolation region.