RECESSED SALICIDE STRUCTURE TO INTEGRATE A FLASH MEMORY DEVICE WITH A HIGH K, METAL GATE LOGIC DEVICE
First Claim
1. An integrated circuit for an embedded flash memory device, said integrated circuit comprising:
- a semiconductor substrate including a memory region and a logic region adjacent to the memory region;
a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9;
a flash memory cell device arranged over the memory region, the flash memory cell device including a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions; and
a silicide contact pad arranged over a top surface of the memory cell gate, wherein the top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions.
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Accused Products
Abstract
An integrated circuit for an embedded flash memory device is provided. A semiconductor substrate includes a memory region and a logic region adjacent to the memory region. A logic device is arranged over the logic region and includes a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9. A flash memory cell device is arranged over the memory region. The flash memory cell device includes a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions. A silicide contact pad is arranged over a top surface of the memory cell gate. The top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions. A method of manufacturing the integrated circuit is also provided.
35 Citations
30 Claims
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1. An integrated circuit for an embedded flash memory device, said integrated circuit comprising:
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a semiconductor substrate including a memory region and a logic region adjacent to the memory region; a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9; a flash memory cell device arranged over the memory region, the flash memory cell device including a memory cell gate electrically insulated on opposing sides by corresponding dielectric regions; and a silicide contact pad arranged over a top surface of the memory cell gate, wherein the top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to a top surface of the metal gate and top surfaces of the dielectric regions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10-19. -19. (canceled)
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20. An integrated circuit for an embedded flash memory device, said integrated circuit comprising:
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a semiconductor substrate including a memory region and a logic region adjacent to the memory region, the memory region including a common source/drain region and a pair of individual source/drain regions arranged on opposite sides of the common source/drain region; a logic device arranged over the logic region and including a metal gate separated from the semiconductor substrate by a material having a dielectric constant exceeding 3.9; and a pair of flash memory cell devices arranged over the memory region, wherein each flash memory cell device corresponds to one of the individual source/drain regions and includes; a select gate and a memory gate arranged between the common source/drain region and the corresponding individual source/drain region; and a charge trapping dielectric arranged between neighboring sidewalls of the memory and select gates, and arranged under the memory gate; and silicide contact pads respectively arranged over top surfaces of the select and memory gates, wherein top surfaces of the silicide contact pads are recessed relative to a top surface of the metal gate and top surfaces of the charge trapping dielectrics - View Dependent Claims (21, 22, 23, 24)
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25. An integrated circuit for an embedded flash memory device, said integrated circuit comprising:
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a flash memory cell device arranged over a semiconductor substrate, the flash memory cell device including a memory cell gate electrically insulated on opposing sides by corresponding dielectric layers; and a silicide contact pad arranged over a top surface of the memory cell gate, wherein the top surface of the memory cell gate and a top surface of the silicide contact pad are recessed relative to top surfaces of the dielectric layers. - View Dependent Claims (26, 27, 28, 29, 30)
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Specification