PIXEL STRUCTURE AND MANUFACTURING METHOD THEREOF

• US 20160013219A1
• Filed: 11/18/2013
• Published: 01/14/2016
• Est. Priority Date: 11/12/2013
• Status: Active Grant

• Current Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Original Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd. (TCL Technology Group Corp.)
• Inventors: HAO, Sikun
• Granted Patent: US 9,685,470 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134372 for fringe field switching [FFS] where the common electrode is not patterned
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1262 with a particular formation, treatment or coating of the substrate

Abstract

The present invention provides a pixel structure and a manufacturing method thereof. The pixel structure includes: a transparent substrate (60), a gate line formed on the transparent substrate (60), a thin-film transistor formed on the transparent substrate (60), a data line (68) formed on the transparent substrate (60), a pixel electrode (62) formed on the transparent substrate (60) and the thin-film transistor, a passivation layer (64) formed on the pixel electrode (62), the transparent substrate (60), and the data line (68), and a common electrode (66) formed on the passivation layer (64). The passivation layer (64) includes: a first portion (72) located on the data line (68), a second portion (74) located on the pixel electrode (62), and a third portion (76) located on the transparent substrate (60) and arranged on two opposite sides of the data line (68). The first portion (72) of the passivation layer (64) has a thickness greater than a thickness of the second portion (74).

Claims

1. A pixel structure, comprising:

a transparent substrate, a gate line formed on the transparent substrate, a thin-film transistor formed on the transparent substrate, a data line formed on the transparent substrate, a pixel electrode formed on the transparent substrate and the thin-film transistor, a passivation layer formed on the pixel electrode, the transparent substrate, and the data line, and a common electrode formed on the passivation layer, the passivation layer comprising;

a first portion located on the data line, a second portion located on the pixel electrode, and a third portion that is located on the transparent substrate and arranged on two opposite sides of the data line, the first portion of the passivation layer having a thickness that is greater than a thickness of the second portion, the pixel electrode and the common electrode partly overlapping so as to form a storage capacitance.

2. The pixel structure as claimed in claim 1, wherein the thickness of the first portion of the passivation layer is greater than a thickness of the third portion and a top of the second portion of the passivation layer is substantially flush with a top of the third portion, the pixel structure further comprising a protective layer formed between the thin-film transistor and the pixel electrode.

3. The pixel structure as claimed in claim 1, wherein the thin-film transistor comprises a gate terminal, a drain terminal, and a source terminal, the gate terminal being electrically connected to the gate line, the source terminal being electrically connected to the data line, and the drain terminal being electrically connected to the pixel electrode, the pixel electrode being a transparent conductive layer, the common electrode being a transparent conductive layer.

4. A manufacturing method of a pixel structure, comprising the following steps:

(11) providing a transparent substrate;

(12) depositing a gate line, a thin-film transistor, a data line, and a pixel electrode on the transparent substrate;

(13) depositing a passivation layer on the transparent substrate, the data line, and the pixel electrode, wherein the passivation layer comprises;

a first portion located on the data line, a second portion located on the pixel electrode, and a third portion located on the transparent substrate and arranged on two opposite sides of the data line;

(14) applying etching to a portion of the passivation layer on a peripheral circuit so as to complete a first time etching and then subjecting the second portion of the passivation layer to etching so as to complete a second time etching to reduce a thickness of the second portion of the passivation layer thereby making a thickness of the first portion of the passivation layer greater than the thickness of the second portion; and

(15) depositing a common electrode on the passivation layer.

5. The manufacturing method of the pixel structure as claimed in claim 4, wherein step (12) further comprises forming a protective layer on the transparent substrate so that the protective layer is arranged between the thin-film transistor and the pixel electrode.

6. The manufacturing method of the pixel structure as claimed in claim 4, wherein the second time etching of step (14) further comprises etching applied to the third portion of the passivation layer so that after the completion of the second time etching, the thickness of the first portion of the passivation layer is greater than the thickness of the third portion and a top of the second portion of the passivation layer is substantially flush with a top of the third portion.

7. The manufacturing method of the pixel structure as claimed in claim 4, wherein the pixel electrode is a transparent conductive layer and the common electrode is a transparent conductive layer.

8. A manufacturing method of a pixel structure, comprising the following steps:

(21) providing a transparent substrate;

(22) depositing a gate line, a thin-film transistor, a data line, and a pixel electrode on the transparent substrate;

(23) depositing a first passivation layer on the transparent substrate, the data line, and the pixel electrode and subjecting the first passivation layer to etching in such a way that only a portion of the first passivation layer that is located on the data line is preserved, while a remaining portion is removed;

(24) depositing a second passivation layer on the transparent substrate, the pixel electrode, and the first passivation layer and subjecting the second passivation layer to etching in such a way that a portion of the second passivation layer on a peripheral circuit is removed, while a remaining portion is preserved; and

(25) depositing a common electrode on the second passivation layer.

9. The manufacturing method of the pixel structure as claimed in claim 8, wherein the first passivation layer has a thickness greater than a thickness of the second passivation layer.

10. The manufacturing method of the pixel structure as claimed in claim 8, wherein step (22) further comprises forming a protective layer on the transparent substrate so that the protective layer is arranged between the thin-film transistor and the pixel electrode, the pixel electrode being a transparent conductive layer, the common electrode being a transparent conductive layer.