THIN FILM TRANSISTOR SUBSTRATE, DISPLAY APPARATUS, METHOD FOR MANUFACTURING THE THIN FILM TRANSISTOR SUBSTRATE, AND METHOD FOR MANUFACTURING THE DISPLAY APPARATUS

• US 20160013323A1
• Filed: 12/10/2014
• Published: 01/14/2016
• Est. Priority Date: 07/08/2014
• Status: Abandoned Application

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KHANG, Yoonho, JEONG, Woonghee, KIM, Myounghwa, SHIN, Youngki, LEE, Kyoungwon
• Application Number:
  US14/565,880
• Publication Number:
  US 20160013323A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1274 using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A thin film transistor substrate includes a substrate, an anodized aluminum layer on the substrate, a polycrystalline silicon layer covering the anodized aluminum layer, and an insulating layer covering the polycrystalline silicon layer.

Claims

1. A thin film transistor substrate, comprising:

a substrate;

an anodized aluminum layer on the substrate, the anodized aluminum layer including a plurality of holes that extend in a direction perpendicular to the substrate and penetrate entirely through the anodized aluminum layer to expose an upper surface of a layer beneath the anodized aluminum layer;

a polycrystalline silicon layer covering the anodized aluminum layer; and

an insulating layer covering the polycrystalline silicon layer.

3. The thin film transistor substrate as claimed in claim 1, wherein the plurality of holes of the anodized aluminum layer contain air.

4. The thin film transistor substrate as claimed in claim 1, wherein:

the insulating layer includes a plurality of through holes that expose the polycrystalline silicon layer, and

the thin film transistor substrate further includes a source electrode and a drain electrode that contact the polycrystalline silicon layer via the through holes.

5. The thin film transistor substrate as claimed in claim 4, wherein the anodized aluminum layer is limited to a source region, a drain region, and an active region of the polycrystalline silicon layer, the source region and the drain region contacting the source electrode and the drain electrode, and the active region being between the source region and the drain region.

6. The thin film transistor substrate as claimed in claim 4, wherein the anodized aluminum layer is limited to an active region of the polycrystalline silicon layer between a source region and a drain region of the polycrystalline silicon layer, the source region and the drain region contacting the source electrode and the drain electrode.

7. The thin film transistor substrate as claimed in claim 1, further comprising an auxiliary buffer layer covering the anodized aluminum layer, wherein the polycrystalline silicon layer is on the auxiliary buffer layer.

2. (canceled)

8. A display apparatus, comprising:

a substrate;

an anodized aluminum layer on the substrate, the anodized aluminum layer including a plurality of holes that extend in a direction perpendicular to the substrate and penetrate entirely through the anodized aluminum layer to expose an upper surface of a layer beneath the anodized aluminum layer;

a polycrystalline silicon layer covering the anodized aluminum layer;

an insulating layer covering the polycrystalline silicon layer, the insulating layer including a plurality of through holes to expose the polycrystalline silicon layer;

a source electrode and a drain electrode contacting the polycrystalline silicon layer via the through holes; and

a pixel electrode electrically connected to any one of the source electrode and the drain electrode.

10. The display apparatus as claimed in claim 8, wherein the plurality of holes of the anodized aluminum layer contain air.

11. The display apparatus as claimed in claim 8, wherein the anodized aluminum layer is limited to a source region, a drain region, and an active region of the polycrystalline silicon layer, the source region and drain region-contacting the source electrode and the drain electrode, the active region being between the source region and the drain region.

12. The display apparatus as claimed in claim 8, wherein the anodized aluminum layer is limited to an active region of the polycrystalline silicon layer between a source region and a drain region of the polycrystalline silicon layer, the source region and the drain region contacting the source electrode and the drain electrode.

13. The display apparatus as claimed in claim 8, further comprising an auxiliary buffer layer covering the anodized aluminum layer, wherein the polycrystalline silicon layer is on the auxiliary buffer layer.

9. (canceled)

14. A method for manufacturing a thin film transistor substrate, the method comprising:

forming an aluminum layer on a substrate;

forming an anodized aluminum layer by anodizing the aluminum layer such that a plurality of holes extending in a direction perpendicular to the substrate and penetrating entirely through the anodized aluminum layer to expose an upper surface of a layer beneath the anodized aluminum layer are formed in the anodized aluminum layer;

forming an amorphous silicon layer to cover the anodized aluminum layer; and

forming a polycrystalline silicon layer by crystallizing the amorphous silicon layer.

16. The method as claimed in claim 14, further comprising forming an auxiliary buffer layer covering the anodized aluminum layer, wherein, in forming the amorphous silicon layer to cover the anodized aluminum layer, the amorphous silicon layer is formed on the auxiliary buffer layer.

17. The method as claimed in claim 14, wherein, in forming the aluminum layer, the aluminum layer is patterned to be limited to a thin film transistor.

18. The method as claimed in claim 14, further comprising patterning the anodized aluminum layer to be limited to a thin film transistor.

15. (canceled)