RECTIFIER CIRCUIT FOR CONVERTING AC VOLTAGE INTO RECTIFIED VOLTAGE

• US 20160013730A1
• Filed: 07/14/2015
• Published: 01/14/2016
• Est. Priority Date: 07/14/2014
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: NERI, FILIPPO
• Application Number:
  US14/799,305
• Publication Number:
  US 20160013730A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 1/0085 Partially controlled bridges
• CPC Class Codes: H02M 1/096 the power supply of the control circuit being connected in parallel to the main switching element H02M1/092 takes precedence
• CPC Class Codes: H02M 7/21 using devices of a triode or transistor type requiring continuous application of a control signal
• CPC Class Codes: H02M 7/217 using semiconductor devices only
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H03K 17/302 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0072 Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0081 Power supply means, e.g. to the switch driver

Abstract

A rectifier circuit includes a low side switching circuit, a high side switching circuit and a low side driver. The low side switching circuit is connected between a reference node and first and second input nodes. The first and second input nodes receive an alternating current (AC) voltage. The high side switching circuit is connected between an output node and the first and second input nodes. The output node outputs a rectified voltage of the AC voltage. The low side driver is coupled to the low side switching circuit. The low side driver controls, in response to a control signal, the low side switching circuit so that the low side driving voltage and a voltage provided from one of the first and second input nodes are synchronized in phase.

Claims

1. A rectifier circuit comprising:

a low side switching circuit connected between a reference node and first and second input nodes, wherein the first and second input nodes receive an alternating current (AC) voltage;

a high side switching circuit connected between an output node and the first and second input nodes, wherein the output node outputs a rectified voltage of the AC voltage; and

a low side driver coupled to the low side switching circuit, wherein the low side driver is configured to control, in response to a control signal, the low side switching circuit so that the low side driving voltage and a voltage provided from one of the first and second input nodes are synchronized in phase.

2. The rectifier circuit of claim 1, wherein the high side switching circuit comprises a diode, and

wherein an anode of the diode is connected to the first input node and a cathode of the diode is connected to the output node.

3. The rectifier circuit of claim 1, wherein the low side switching circuit comprises a switching transistor and a diode connected in parallel between the reference node and the first input node.

4. The rectifier circuit of claim 3, wherein a gate terminal of the switching transistor is coupled to the low side driver, receiving the low side driving voltage.

5. A rectifier circuit comprising:

a low side switching circuit connected between a reference node and first and second input nodes, wherein the first and second input nodes receive an alternating current (AC) voltage;

a high side switching circuit connected between an output node and the first and second input nodes, wherein the output node outputs a rectified voltage of the AC voltage;

first and second low side drivers, each being coupled to the low side switching circuit, wherein the first and second low side drivers are configured to generate low side driving voltages, and wherein the first and second low side drivers are configured to control, in response to a control signal, the low side switching circuit so that the low side driving voltages provided from the first and second low side drivers are synchronized with voltages provided from the second and first input nodes, respectively;

a bootstrap circuit coupled to the second input node, wherein the bootstrap circuit is configured to generate a bootstrapping voltage based on a bootstrap driving voltage and the voltage provided from the second input node; and

a high side driver coupled to the high side switching circuit, wherein the high side driver is configured to provide a high side driving voltage to the high side switching circuit to control the high side switching circuit and generate the high side driving voltage based on at least one of the rectified voltage, the voltages provided from the first and second input nodes, the low side driving voltage generated by the second low side driver, the bootstrap driving voltage, and the bootstrapping voltage.

6. The rectifier circuit of claim 5, wherein high side driving voltage is greater than the low side driving voltage by the bootstrap driving voltage.

7. The rectifier circuit of claim 5, wherein the bootstrap circuit comprises a diode and a capacitor

connected in series between a node where the bootstrap driving voltage is applied and the second input node, and

wherein the bootstrapping voltage is outputted from a node at which the diode and the capacitor are connected to each other.

8. The rectifier circuit of claim 7, wherein an anode of the diode is connected to the node where the bootstrap driving voltage is applied,

wherein one terminal of the capacitor is connected to the second input node, and

wherein a cathode of the diode is connected to another terminal of the capacitor.

9. The rectifier circuit of claim 5, wherein the low side switching circuit comprises a low side transistor, one terminal of the low side transistor being connected to the reference node, another terminal of the low side transistor being connected to the first input node, and

wherein the high side switching circuit comprises a high side transistor, one terminal of the high side transistor being connected to the first input node, another terminal of the high side transistor being connected to the output node.

10. The rectifier circuit of claim 9, wherein a gate terminal of the low side transistor is coupled to the first low side driver, receiving the low side driving voltage from the first low side driver, and

wherein a gate terminal of the high side transistor is coupled to the high side driver, receiving the high side driving voltage from the high side driver.

11. The rectifier circuit of claim 9, wherein the high side driver comprises:

a level shifter configured to generate the high side driving voltage based on the voltage provided from the first input node, the low side driving voltage, and the bootstrapping voltage;

a latch circuit configured to latch the high side driving voltage;

a pull-up signal generator configured to generate a pull-up signal based on the high side driving voltage and the latched high side driving voltage; and

a pull-up circuit configured to control the level shifter so that the level shifter generates, in response to the pull-up signal, the high side driving voltage.

12. The rectifier circuit of claim 9, wherein the high side driver comprises:

a bias current generator configured to receive the bootstrap driving voltage to generate a bias current;

a current mode comparator configured to generate a comparison signal based on an amplitude comparison result of the voltage provided from the first input node and the rectified voltage, by using the generated bias current; and

a level shifter configured to generate an intermediate signal, based on the generated comparison signal.

13. The rectifier circuit of claim 12, wherein the bias current generator comprises a first-type first current mirror configured to provide the bias current to the current mode comparator.

14. The rectifier circuit of claim 13, wherein the current mode comparator comprises:

a second-type first current mirror configured to output current provided from the first-type first current mirror, by using the rectified voltage;

a first-type second current mirror configured to output current provided from the second-type first current mirror;

a second-type second current mirror configured to output current provided from the first-type second current mirror, by using the voltage provided from the first input node; and

a first-type third current mirror configured to output current provided from the second-type second current mirror,

wherein the comparison signal is generated based on the current outputted from the second-type first current mirror and current outputted from the first-type third current mirror.

15. The rectifier circuit of claim 14, wherein the level shifter comprises:

a first-type fourth current mirror coupled to the second-type first current mirror;

a comparison control transistor coupled to the first-type fourth current mirror, wherein a gate terminal of the comparison control transistor receives the comparison signal;

a second-type third current mirror coupled between the comparison control transistor and the second input node;

a second-type fourth current mirror coupled between the first-type fourth current mirror and the second input node; and

a first-type fifth current mirror coupled between the second-type fourth current mirror and the first input node,

wherein the intermediate signal is generated based on current outputted from the second-type third current mirror and current outputted from the first-type fifth current mirror.

16. The rectifier circuit of claim 15, wherein each of the first-type first current mirror, the first-type second current mirror, the first-type third current mirror, the first-type fourth current mirror, and the first-type fifth current mirror is an n-channel metal oxide semiconductor (NMOS) type current mirror, and

wherein each of the second-type first current mirror, the second-type second current mirror, the second-type third current mirror, and the second-type fourth current mirror is a p-channel metal oxide semiconductor (PMOS) type current mirror.

17. The rectifier circuit of claim 12, wherein the high side driver further comprises:

an inverter configured to invert the intermediate signal; and

an output circuit configured to output the inverted intermediate signal as the high side driving voltage.

18. A rectifier circuit comprising:

a low side switching circuit connected between a reference node and first and second input nodes, wherein the first and second input nodes receive an alternating current (AC) voltage;

a high side switching circuit connected between an output node and the first and second input nodes, wherein the output node outputs a rectified voltage of the AC voltage;

first and second low side drivers, each being coupled to the low side switching circuit, wherein the first and second low side drivers are configured to generate low side driving voltages, and wherein the first and second low side drivers are configured to control, in response to a control signal, the low side switching circuit so that the low side driving voltages provided from the first and second low side drivers are synchronized with voltages provided from the second and first input nodes, respectively;

a bootstrap driving voltage generator configured to generate a bootstrap driving voltage based on the rectified voltage, the control signal, and an offset voltage; and

a bootstrap circuit coupled to the high side switching circuit, wherein the bootstrap circuit is configured to generate a bootstrapping voltage based on the low side driving voltage generated by the first low side driver and the bootstrap driving voltage and provide the bootstrapping voltage to the high side switching circuit.

19. The rectifier circuit of claim 18, further comprising a substrate voltage generator configured to generate a substrate voltage applied to a substrate of a high side transistor included in the high side switching circuit, by using the voltages provided from the first and second input nodes.

20. The rectifier circuit of claim 18, wherein a value of the offset voltage is adjustable, and

wherein a value of the generated bootstrap driving voltage corresponds to a value obtained by adding the value of the offset voltage to a value obtained by subtracting a value of the voltage corresponding to the control signal from a value of the rectified voltage.