GATE DRIVE UNDER-VOLTAGE DETECTION

• US 20160018446A1
• Filed: 07/15/2014
• Published: 01/21/2016
• Est. Priority Date: 07/15/2014
• Status: Active Grant

• Current Assignee: Ford Global Technologies, LLC (Ford Motor Company)
• Original Assignee: Ford Global Technologies, LLC (Ford Motor Company)
• Inventors: Chen, Lihua, Cao, Dong, Zhou, Yan, Rogers, Craig
• Granted Patent: US 9,322,852 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 19/1659 to indicate that the value is within or outside a predetermined range of values (window) G01R19/16514, G01R19/16519, G01R19/16528 and G01R19/16533 take precedence
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 7/53871 with automatic control of output voltage or current
• CPC Class Codes: H03K 17/00 Electronic switching or gating, i.e. not by contact-making and –breaking gated amplifiers H03F3/72; switching arrangements for exchange systems using static devices H04Q3/52
• CPC Class Codes: H03K 17/18 Modifications for indicating state of switch

Abstract

Gate drive faults are detected for an inverter which comprises a phase switch having an insulated gate, such as an IGBT. A complementary transistor pair is adapted to receive a supply voltage and a pulse-width modulated (PWM) signal to alternately charge and discharge the insulated gate. A comparator compares the voltage at the insulated gate with a reference voltage representing a gate drive fault to generate a first logic signal. A latch samples the first logic signal when the PWM signal has a value corresponding to charging the insulated gate. A logic circuit inhibits charging of the insulated gate when the latched logic signal indicates the gate drive fault. An insulated gate voltage less than the reference voltage is indicative of an under-voltage fault as well as other device failures of the IGBT or the complementary transistors.

Claims

1. An inverter comprising:

a phase switch having an insulated gate;

a complementary transistor pair adapted to receive a supply voltage and a PWM signal to alternately charge and discharge the insulated gate;

a comparator comparing a voltage at the insulated gate with a reference voltage representing a gate drive fault to generate a first logic signal;

a latch sampling the first logic signal when the PWM signal has a value corresponding to charging the insulated gate; and

a logic circuit inhibiting charging of the insulated gate when the latched logic signal indicates the gate drive fault.

2. The inverter of claim 1 wherein the gate drive fault is an under-voltage fault of the supply voltage.

3. The inverter of claim 2 wherein the reference voltage is configured to indicate the under-voltage fault whenever the supply voltage is less than 90% of a target value.

4. The inverter of claim 1 wherein the gate drive fault includes an insulation fault of the insulated gate and a conduction fault of the complementary transistor pair.

5. The inverter of claim 1 wherein the latch is triggered by a falling edge of the PWM signal.

6. The inverter of claim 1 further comprising a second comparator for comparing a voltage across the phase switch to a second reference voltage indicative of an On state of the phase switch, wherein the latch is triggered by the second comparator when the on state is detected.

7. The inverter of claim 1 wherein the latch is comprised of a D-type flip-flop.

8. A method of detecting a gate drive fault of an insulated gate phase switch in an inverter of an electrified vehicle, comprising:

coupling a PWM signal to a complementary transistor pair to alternately charge and discharge the insulated gate of the phase switch during charge and discharge phases of the PWM signal, respectively;

comparing a voltage at the insulated gate to a reference voltage representing a gate drive fault to generate a first logic signal;

latching the first logic signal once during the charge phase of the PWM signal; and

inhibiting the charging of the insulated gate after the latched logic signal indicates the gate drive fault.

9. The method of claim 8 wherein the gate drive fault is an under-voltage fault of the supply voltage, and wherein the reference voltage is configured to indicate the under-voltage fault whenever the supply voltage is less than 90% of a target value.

10. The method of claim 8 wherein the gate drive fault includes an insulation fault of the insulated gate and a conduction fault of the complementary transistor pair.

11. The method of claim 8 wherein the latching step is triggered by a falling edge of the PWM signal.

12. The method of claim 8 further comprising the step of:

comparing a voltage across the phase switch to a second reference voltage indicative of an on state of the phase switch;

wherein the latching step is triggered by the second comparator when the on state is detected.

13. An under-voltage detector comprising:

an inverter phase switch having an insulated gate;

a transistor pair using a supply voltage to charge and discharge the gate;

a comparator generating a logic signal when a gate voltage is less than a reference;

a latch for sampling the logic signal during charging of the gate; and

a logic circuit inhibiting charging of the gate when the latched logic signal indicates an under-voltage of the gate.