TIME MULTIPLEXING AT DIFFERENT RATES TO ACCESS DIFFERENT MEMORY TYPES
First Claim
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1. A memory system, comprising:
- a signal bus;
a plurality of memory devices of different types coupled in parallel to the signal bus; and
,a component coupled to the signal bus, and configured to time division multiplex data for the different types of memory devices on the signal bus such that the data is output on the signal bus at different clock rates for the different types of memory devices.
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Abstract
A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.
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Citations
20 Claims
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1. A memory system, comprising:
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a signal bus; a plurality of memory devices of different types coupled in parallel to the signal bus; and
,a component coupled to the signal bus, and configured to time division multiplex data for the different types of memory devices on the signal bus such that the data is output on the signal bus at different clock rates for the different types of memory devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory component, comprising:
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a first interface configured to couple a first clock signal having a first clock rate to at least one memory device of a first type; a second interface configured to couple a second clock signal having a second clock rate to at least one memory device of a second type; and
,a third interface configured to time division multiplex data communicated with the first type of memory device and the second type of memory device such that the data is communicated via the third interface at different clock rates for the first type of memory device and the second type of memory device. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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20. A memory system, comprising:
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means for transferring data over a shared signal bus in a time division multiplexed manner at different rates by providing a first clock signal having a first clock rate for a first set of data transfers and providing a second clock signal having a second clock rate for a second set of data transfers; means for using the first clock signal during the first set of data transfers to transfer a first portion of the data between the shared signal bus and a first type of memory device of a plurality of memory devices of different types coupled in parallel to the signal bus; and
,means for using the second clock signal during the second set of data transfers to transfer a second portion of the data between the shared signal bus and a second type of memory device of the different types of memory devices.
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Specification