SHIFT REGISTER AND METHOD OF DRIVING SHIFT REGISTER

• US 20160019828A1
• Filed: 07/20/2015
• Published: 01/21/2016
• Est. Priority Date: 07/18/2014
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Lin, Wei-Li, Tung, Che-Wei, Chen, Chia-Heng
• Granted Patent: US 9,626,890 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/0214 with crosstalk due to leakage current of pixel switch in active matrix panels
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register includes a plurality of stages of shift register circuit. Each stage of shift register circuit includes a first switch, an input circuit, a pull-down circuit, and a pull-down voltage regulator circuit. The first switch is used to output a scan signal according to a voltage level of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a signal from a previous M-th stage of shift register circuit. The pull-down circuit is used to pull down the voltage level of the node according to the clock signal and a signal from a following L-th shift register circuit and reduce current leakage at the node. The pull-down voltage regulator circuit is used to pull down the voltage levels of the node and the scan signal according to the voltage level of the node.

Claims

1. A shift register comprising a plurality of stages of shift register circuit, wherein each stage of shift register circuit comprises:

a first switch having a first terminal for receiving a clock signal, a second terminal for outputting a first scan signal of current stage of shift register circuit, and a control terminal electrically coupled to a node of the current stage of shift register circuit;

an input circuit comprising;

a second switch having a first terminal, a second terminal electrically coupled to the node of the current stage of shift register circuit, and a control terminal electrically coupled to a node of a previous M-th stage of shift register circuit in the plurality of stages of shift register circuit, wherein M is a positive integer; and

a receiving circuit electrically coupled to the first terminal of the second switch, for receiving a scan signal outputted from the previous M-th stage of shift register circuit, and for controlling a voltage level of the first terminal of the second switch according to the scan signal;

a pull-down circuit electrically coupled to the node of the current stage of shift register circuit and for pulling down a voltage level of the node of the current stage of shift register circuit according to a scan signal outputted from a following L-th stage of shift register circuit in the plurality of stages of shift register circuit, wherein L is a positive integer; and

a pull-down voltage regulator circuit electrically coupled to the node of the current stage of shift register circuit and the second terminal of the first switch and for pulling down a voltage level of the second terminal of the first switch according to the voltage level of the node of the current stage of shift register circuit.

2. The shift register of claim 1, wherein each stage of shift register circuit further comprises:

a third switch having a first terminal for receiving the clock signal, a second terminal for outputting a second scan signal, and a control terminal electrically coupled to the node of the current stage of shift register circuit;

wherein the receiving circuit for receiving the scan signal outputted from the previous M-th stage of shift register circuit is to receive a first scan signal outputted from the previous M-th stage of shift register circuit or a second scan signal outputted from the previous M-th stage of shift register circuit, and the pull-down circuit for pulling down the voltage level of the node of the current stage of shift register circuit according to the scan signal outputted from the following L-th stage of shift register circuit is to receive a first scan signal outputted from the following L-th stage of shift register circuit or a second scan signal outputted from the following L-th stage of shift register circuit.

3. The shift register of claim 1, wherein the pull down circuit of each stage of shift register circuit comprises:

a fourth switch having a first terminal electrically coupled to the node of the current stage of shift register circuit, a second terminal electrically coupled to the second terminal of the first switch, and a control terminal;

a capacitor having a first terminal for receiving the clock signal and a second terminal electrically coupled to the control terminal of the fourth switch; and

a fifth switch having a first terminal for receiving the scan signal outputted from the following L-th stage of shift register circuit, a second terminal electrically coupled to the second terminal of the capacitor, and a control terminal electrically coupled to the first terminal of the fifth switch.

4. A shift register comprising a plurality of stages of shift register circuit, wherein each stage of shift register circuit comprises:

an input circuit for receiving a scan signal outputted from a previous M-th stage of shift register circuit and for pulling up a voltage level of a node of current stage of shift register circuit according to the scan signal;

a first switch having a first terminal for receiving a clock signal, a second terminal for outputting a first scan signal of the current stage of shift register circuit, and a control terminal electrically coupled to the node of the current stage of shift register circuit;

a pull-down circuit comprising;

a second switch having a first terminal electrically coupled to the node of the current stage of shift register circuit, a second terminal electrically coupled to the second terminal of the first switch, and a control terminal;

a pull-down controlling circuit for receiving the clock signal and a scan signal outputted from a following L-th stage of shift register circuit and for controlling a voltage level of the control terminal of the second switch according to the clock signal and the scan signal outputted from the following L-th stage of shift register circuit, wherein L is a positive integer; and

a first pull-down voltage regulator circuit electrically coupled to the node of the current stage of shift register circuit, the second terminal of the first switch and a node of the following L-th stage of shift register circuit, and for pulling down a voltage level of the second terminal of the first switch according to the voltage level of the node of the current stage of shift register circuit and a voltage level of the node of the following L-th stage of shift register circuit.

5. The shift register of claim 4, wherein each stage of shift register circuit further comprises:

a third switch having a first terminal for receiving the clock signal, a second terminal for outputting a second scan signal, and a control terminal electrically coupled to the node of the current stage of shift register circuit;

wherein the input circuit for receiving the scan signal outputted from the previous M-th stage of shift register circuit is to receive a first scan signal outputted from the previous M-th stage of shift register circuit or a second scan signal outputted from the previous M-th stage of shift register circuit, and the pull-down controlling circuit for receiving the scan signal outputted from the following L-th stage of shift register circuit is to receive a first scan signal outputted from the following L-th stage of shift register circuit or a second scan signal outputted from the following L-th stage of shift register circuit.

6. The shift register of claim 4, wherein the input circuit comprises:

a fourth switch having a first terminal, a second terminal electrically coupled to the node of the current stage of shift register circuit, and a control terminal electrically coupled to a node of the previous M-th stage of shift register circuit; and

a receiving circuit for receiving the scan signal outputted from the previous M-th stage of shift register circuit, and for reducing a voltage level difference between the first terminal of the fourth switch and the node of the current stage of shift register circuit and for making a voltage level of the control terminal of the fourth switch equal to a voltage level of the first terminal of the fourth switch when the first scan signal is of the high voltage level.

7. The shift register of claim 4, wherein the pull-down controlling circuit comprises:

a capacitor having a first terminal for receiving the clock signal and a second terminal electrically coupled to the control terminal of the second switch; and

a fifth switch having a first terminal for receiving the scan signal outputted from the following L-th stage of shift register circuit, a second terminal electrically coupled to the second terminal of the capacitor, and a control terminal electrically coupled to the first terminal of the fifth switch.

8. The shift register of claim 4, further comprising:

a second pull-down voltage regulator circuit electrically coupled to the node of the current stage of shift register circuit, the second terminal of the first switch, a second enabling signal and the node of the following L-th stage of shift register circuit, and for pulling down the voltage level of the node of the current stage of the shift register circuit and the voltage level of the second terminal of the first switch according to a voltage level of the second enabling signal, the voltage level of the node of the current stage of shift register circuit and the voltage level of the node of the following L-th stage of shift register circuit;

wherein the first pull-down voltage regulator circuit further receives a first enabling signal and for pulling down the voltage level of the node of the current stage of shift register circuit and the voltage level of the second terminal of the first switch according to the first enabling signal, and the first enabling signal and the second enabling signal are complementary to each other.

9. The shift register of claim 4, wherein the first pull-down voltage regulator circuit comprises:

a sixth switch having a first terminal for receiving a first enabling signal, a second terminal, and a control terminal electrically coupled to the first terminal of the sixth switch;

a seventh switch having a first terminal for receiving the first enabling signal, a second terminal, and a control terminal electrically coupled to the second terminal of the sixth switch;

an eighth switch having a first terminal electrically coupled to the second terminal of the sixth switch, a second terminal electrically coupled to a system voltage terminal, and a control terminal electrically coupled to the node of the following L-th stage of shift register circuit;

a ninth switch having a first terminal electrically coupled to the second terminal of the seventh switch, a second terminal electrically coupled to the system voltage terminal, and a control terminal electrically coupled to the node of following L-th stage of the shift register circuit;

a tenth switch having a first terminal electrically coupled to the control terminal of the second switch, a second terminal electrically coupled to the system voltage terminal, and a control terminal electrically coupled to the second terminal of the seventh switch;

wherein the eighth switch and the ninth switch pull down a voltage level of the second terminal of the seventh switch to prevent the tenth switch from pulling down the voltage level of the control terminal of the second switch when the scan signal of the following L-th stage of shift register circuit is of the high voltage level.

10. A method of driving a shift register, the method comprising:

providing the shift register comprising a plurality of stages of shift register circuit, each stage of shift register circuit comprising an input circuit, a first switch, a capacitor, a pull-down circuit and a pull-down voltage regulator circuit, the first switch having a control terminal electrically coupled to the input circuit, a first terminal, and a second terminal, the capacitor having a first terminal electrically coupled to the control terminal of the first switch, a second terminal electrically coupled the second terminal of the first switch, the pull-down circuit comprising a pull-down controlling circuit and a second switch, the second switch having a first terminal electrically coupled to the control terminal of the first switch, a second terminal electrically coupled to the second terminal of the first switch, and a control terminal electrically coupled to the pull-down controlling circuit, the pull-down voltage regulator circuit electrically coupled to the second terminal and the control terminal of the first switch;

receiving, by the input circuit, a scan signal having a first high voltage level outputted from a previous M-th stage of shift register circuit to enable the input circuit to pull up a voltage level of the control terminal of the first switch, wherein M is a positive integer;

receiving, by the first terminal of the first switch and the pull-down controlling circuit, a clock signal having the first high voltage level to enable;

the second terminal of the first switch to output a scan signal having the first high voltage level;

the capacitor to couple the voltage level of the control terminal of the first switch to a second high voltage level, wherein the second high voltage level is higher than the first high voltage level; and

the pull-down controlling circuit to pull up a voltage level of the control terminal of the second switch; and

enabling the clock signal to have a low voltage level to enable;

the second terminal of the first switch to be pulled down to the low voltage level; and

the capacitor to pull down the voltage level of the control terminal of the first switch.

11. The method of claim 10, wherein the pull-down voltage regulator circuit of each stage of shift register circuit is further electrically coupled to the control terminal of the second switch and a control terminal of a first switch of a following L-th stage of shift register circuit, L is a positive integer, the method further comprising:

receiving, by the pull-down controlling circuit, a scan signal having the first high voltage level outputted from the following L-th stage of shift register circuit to enable the pull-down voltage regulator circuit to stop pulling down the voltage level of the control terminal of the second switch to the low voltage level and to enable the second switch to pull down the voltage level of the control terminal of the first switch of the current stage of shift register circuit.