SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SAME

• US 20160019975A1
• Filed: 06/18/2015
• Published: 01/21/2016
• Est. Priority Date: 07/21/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KANG, DONG-KU, YU, JAE-DUK, LEE, DAE-YEAL
• Granted Patent: US 9,478,280 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence

Abstract

A semiconductor memory device is configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period. The semiconductor memory device includes a memory cell array that stores program data, a sensor generating sensing data, and a condition determination unit comparing the program data and the sensing data. A control logic unit includes a verification operation controller configured to selectively perform, based on a result of comparison of the program data and the sensing data, a first verification control operation for controlling a second verification operation by setting the initial voltage level to a second voltage level and boosting the verification voltage during a second period, and a second verification control operation for controlling the second verification operation by setting the initial voltage level to the first voltage level and boosting the verification voltage during the first period.

Claims

1. A semiconductor memory device configured to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period, the semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cells configured to store program data;

a sensor configured to generate sensing data by sensing the program data from the memory cell array;

a condition determination unit configured to compare the program data and the sensing data; and

a control logic unit comprising a verification operation controller configured to selectively perform, based on a result of the comparison of the program data and the sensing data, a first verification control operation for controlling a second verification operation by setting the initial voltage level to a second voltage level and boosting the verification voltage during a second period, and a second verification control operation for controlling the second verification operation by setting the initial voltage level to the first voltage level and boosting the verification voltage during the first period.

2. The semiconductor memory device of claim 1, wherein the first period and the second period are the same length.

3. The semiconductor memory device of claim 1, wherein program data stored in one memory cell of the plurality of memory cells is at least 2 bits.

4. The semiconductor memory device of claim 1, wherein the program data is programmed to the plurality of memory cells using an incremental step pulse programming (ISPP) process.

5. The semiconductor memory device of claim 1, wherein the second voltage level is higher than the first voltage level.

6. The semiconductor memory device of claim 1, wherein the condition determination unit comprises:

a verification unit configured to perform the comparison of the program data and the sensing data; and

an identification code generator configured to generate an identification code based on the result of the comparison and transmit the identification code to the control logic unit.

7. The semiconductor memory device of claim 6, wherein a number of bits of the identification code is set based on a number of types of program states stored in each of the plurality of memory cells.

8. The semiconductor memory device of claim 1, wherein the verification operation controller is configured to generate a control signal for setting a magnitude of the second voltage level based on the result of comparison of the program data and the sensing data;

and further comprising a voltage generator configured to set the initial voltage level to the second voltage level having the magnitude based on the control signal and boosting the initial voltage level during the second period and apply the verification voltage to a word line connected to each of the plurality of memory cells.

9. The semiconductor memory device of claim 8, wherein the voltage generator comprises:

a program voltage generator configured to generate a program voltage when a programming operation is performed and apply the program voltage by controlling a first switch; and

a verification voltage generator configured to generate a verification voltage when a verification operation is performed and apply the verification voltage to the word line by controlling a second switch.

10. The semiconductor memory device of claim 9, wherein the verification operation controller is configured to apply the verification voltage to the word line by turning off the first switch and turning on the second switch when a voltage of the word line is reduced to the second voltage level from a level of the program voltage.

11. The semiconductor memory device of claim 9, wherein the verification operation controller further comprises:

a timing controller configured to control on and off timings of the first and second switches; and

an initial voltage controller configured to control a setting operation of an initial voltage level of the verification voltage generator.

12. The semiconductor memory device of claim 11, wherein when the program voltage generator generates and applies the program voltage to each of the plurality of memory cells, the timing controller turns off the first switch when the program voltage is converted to the first voltage level;

wherein the verification voltage generator is configured to turn on the second switch when the first switch is off; and

wherein the initial voltage controller is configured to set the initial voltage level to the first voltage level.

13. The semiconductor memory device of claim 11, wherein when the program voltage generator generates and applies the program voltage to each of the plurality of memory cells, the timing controller turns off the first switch when the program voltage is converted to the second voltage level;

wherein the verification voltage generator is configured to turn on the second switch when the first switch is off; and

wherein the initial voltage controller is configured to set the initial voltage level to the second voltage level.

14. The semiconductor memory device of claim 1, wherein the semiconductor memory device is a flash memory device.

15. A semiconductor memory device configured to perform a plurality of programming loops including a programming operation and a verification operation, the semiconductor memory device comprising:

a control logic unit comprising a verification operation controller configured to selectively perform, based on a result of a comparison of program data and sensing data, a first verification control operation for controlling a second verification operation by setting an initial voltage level to a second voltage level and boosting a verification voltage during a second period, and a second verification control operation for controlling the second verification operation by setting the initial voltage level to a first voltage level and boosting the verification voltage during the first period.

16. A method of operating a semiconductor memory device to perform a first verification operation by setting an initial voltage level of a verification voltage to a first voltage level and boosting the verification voltage during a first period, the method comprising:

storing program data in a plurality of memory cells of a memory cell array;

sensing the program data from the memory cell array to generate sensing data;

comparing the program data and the sensing data; and

selectively performing, based on a result of the comparison of the program data and the sensing data, a first verification control operation for controlling a second verification operation by setting the initial voltage level to a second voltage level and boosting the verification voltage during a second period, and a second verification control operation for controlling the second verification operation by setting the initial voltage level to the first voltage level and boosting the verification voltage during the first period.

17. The method of claim 16, wherein the first period and the second period are the same length.

18. The method of claim 16, wherein storing the program data comprises programming the plurality of memory cells using an incremental step pulse programming (ISPP) process.

19. The method of claim 16, wherein comparing comprises:

performing the comparison of the program data and the sensing data; and

generating an identification code based on the result of the comparison.

20. The method of claim 19, wherein a number of bits of the identification code is set based on a number of types of program states stored in each of the plurality of memory cells.