Non-Circular Die Package Interconnect

• US 20160020192A1
• Filed: 07/17/2014
• Published: 01/21/2016
• Est. Priority Date: 07/17/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Dropps, Frank
• Granted Patent: US 9,305,901 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/245 Material
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49174 Stacked arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/5328 containing conductive organic materials or pastes, e.g. conductive adhesives, inks
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1434 : Memory

Abstract

A computing component may consist of a die package that has at least a board, first computing layer, and second computing layer. Dielectric layers can separate each of the board, first computing layer, and second computing layer. The first computing layer may be disposed between the board and second computing layer. One or more interconnects can continuously extend from the second computing layer to the board with a non-circular cross-section shape.

Claims

1. An apparatus comprising:

a die package comprising a board, first die layer, and second die layer each separated by a dielectric layer, the first die layer disposed between the board and second die layer; and

an interconnect comprising a conductive polymer and continuously extending from the second die layer to the board with a non-circular cross-section shape.

2. The apparatus of claim 1, in which the first and second die layers comprise a first die stack positioned on a first side of the board, a second die stack comprising at least third and fourth die layers comprise a second die stack, the second die stack positioned on a second side of the board, opposite the first side.

3. The apparatus of claim 1, in which the first and second die layers vertically aligned with at least two outer edges aligned along different planes, the different planes each perpendicular to the board.

4. The apparatus of claim 1, in which the interconnect comprises a flexible material.

6. The apparatus of claim 1, in which the conductive polymer comprises metal particles.

7. The apparatus of claim 1, in which the first and second die layers are stacked vertically to form uniform outer edges, the interconnect extending in continuous contact with at least one outer edge.

8. The apparatus of claim 7, in which the interconnect continuously extends around a corner defined by a junction of two uniform outer edges of the first die layer.

9. The apparatus of claim 1, in which the interconnect comprises linear exterior surfaces from the board to the second die layers.

5. (canceled)

10. An apparatus comprising:

a die package comprising a board, first die layer, and second die layer positioned in a vertically aligned stack with at least one common edge surface, the board and first and second die layers each separated by a dielectric layer and having a common width and length, the first die layer disposed between the board and second die layer; and

a first interconnect continuously extending from the second die layer to the board with a non-circular cross-section shape; and

a second interconnect continuously extending from the first die layer to the board with a non-circular cross-section shape, the first interconnect positioned between the first die layer and the second interconnect.

11. The apparatus of claim 10, in which the first and second interconnects are physically separate and overlap.

12. The apparatus of claim 11, in which the first and second interconnects are separated by a dielectric material.

13. The apparatus of claim 11, in which the second interconnect extends farther from the board than the first interconnect.

14. The apparatus of claim 10, in which a third interconnect continuously extends from the board to a third die layer with a non-circular cross-section shape.

15. The apparatus of claim 10, in which the first and second interconnects are respectively positioned on different outer surfaces of the die layers.

16. The apparatus of claim 10, in which the first and second interconnects have a common length and dissimilar pathways.

21. The apparatus of claim 10, wherein the first interconnect continuously contacts an outer edge of the die package and the second interconnect separated from the outer edge of the die package by the first interconnect.

17. A method comprising:

separating a board, first die layer, and second die layer each with a dielectric layer to form a die package, the first die layer disposed between the board and second die layer; and

printing an interconnect with a conductive polymer having a non-circular cross-section shape onto the die package, the interconnect continuously extending from the second die layer to the board.

18. The method of claim 17, in which the interconnect is printed with a three dimensional printer.

19. The method of claim 17, in which the interconnect is printed with a silkscreen process.

20. The method of claim 17, in which the interconnect is printed with at least one right angle turn.