Semiconductor Device Comprising a Plurality of Transistor Cells and Manufacturing Method

• US 20160020315A1
• Filed: 07/02/2015
• Published: 01/21/2016
• Est. Priority Date: 07/15/2014
• Status: Abandoned Application

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz
• Application Number:
  US14/790,665
• Publication Number:
  US 20160020315A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device comprises a plurality of transistor cells. Each one of the plurality of transistor cells comprises a trench extending into a drift zone of a semiconductor body from a first surface, the drift zone being of a first conductivity type. The semiconductor device further comprises a gate electrode structure. A field electrode structure and a first dielectric structure are in the trench. A doped region is embedded in the drift zone lining a bottom side of the trench. The doped region is one of a first conductivity type having a doping concentration lower than the drift zone, and a second conductivity type complementary to the first conductivity type.

Claims

1. A semiconductor device (100), comprising a plurality of transistor cells (1001, 1002), each transistor cell (1001, 1002) comprising

a trench (114) extending into a drift zone (110) of a semiconductor body (102) from a first surface (104), the drift zone (110) being of a first conductivity type;

a gate electrode structure (124);

a field electrode structure (122) and a first dielectric structure (126) in the trench (114);

a doped region (136) surrounded by the drift zone (110) and lining a bottom side of the trench (114), wherein the doped region (136) is of a first conductivity type having a doping concentration lower than the drift zone, and wherein the first dielectric structure (126) includes a field dielectric part (128) between each one of opposite sidewalls of the trench (114) and the field electrode structure (122), and a gate dielectric part (132) between each one of opposite sidewalls of the trench (114) and the gate electrode structure (124), wherein a thickness of the gate dielectric part (132) is smaller than a thickness of the field dielectric part (128).

2. The semiconductor device (100) of claim 1, wherein the doped region (136) abuts the bottom side of the trench (114).

3. The semiconductor device of claim 1, wherein a width of the doped region (136) along a direction parallel to the first surface is in a range of 0.2 μ

m to 2 μ

m.

4. The semiconductor device of claim 1, wherein the drift zone (210) comprises a first region (210a) with a first doping concentration and a second region (210b) with a second doping concentration higher than the first doping concentration, the first region (210a) being arranged between the second region (210b) and the first surface (204), and wherein the doped region (236) is arranged in the second region (210b) of the drift zone (210).

5. The semiconductor device of claim 1, wherein the first dielectric structure (326) in the trench (314) includes a first part (328) between each one of opposite sidewalls of the trench (314) and the field electrode structure (322), and a second part (330) between a bottom side of the trench (314) and the field electrode structure (322), the first part (328) having a first thickness d₁ in a direction parallel to the first surface (304) and the second part (330) having a second thickness d₂ in a direction perpendicular to the first surface (304), the first thickness being smaller than the second thickness.

6. The semiconductor device of claim 5, wherein d₂>

2×

d₁.

7. The semiconductor device of claim 5, wherein the second part (330) of the first dielectric structure (326) is a stacked structure of a plurality of layers of electrically insulating materials.

8. The semiconductor device of claim 1, wherein the gate electrode structure (324) is in the trench (314), and the field electrode structure (322) is arranged between the gate electrode structure (324) and a bottom side of the trench (314).

9. The semiconductor device of claim 1, wherein the gate electrode structure (524) is in the trench (514), the gate electrode structure (524) being arranged adjacent to the field electrode structure (522) in a direction parallel to the first surface (504).

10. The semiconductor device of claim 9, wherein the gate electrode structure (524) comprises first and second sub gate electrodes opposite to each other, the field electrode structure (522) being at least partly arranged between the first and second sub gate electrodes.

11. The semiconductor device of claim 1, wherein the gate electrode structure is a planar gate electrode structure on the semiconductor body at the first surface.

12. The semiconductor device of claim 1, wherein the field electrode structure (622) is arranged in a first trench (614) and the gate electrode structure (624) is arranged in a second trench (615) adjacent to the first trench (614), the first and second trenches (614, 615) extending into the drift zone (610) of the semiconductor body (602), a source region (616) and a body region (608) being arranged between the first and second trenches (614, 615).

13. The semiconductor device of claim 1, further comprising a structure (440) in the trench (414) between the field electrode structure (422) and a bottom side of the trench (414), wherein the structure (440) is surrounded by the first dielectric structure (426).

14. The semiconductor device of claim 13, wherein the structure (440) is one of a dielectric material other than the first dielectric structure, a void and a conductive material.

15. The semiconductor device of claim 1, wherein a vertical distance (l₁) between a bottom side of the trench (114) to one of a field stop zone and a highly doped drain region (112) is less than a lateral distance (l₂) between trenches of adjacent two of the plurality of transistor cells (1001, 1002).

19. A switched-mode power supply device, comprising the semiconductor device of claim 1.

20. The switched-mode power supply device of claim 19, wherein the switched-mode power supply device is a resonant switched-mode power supply device.

16. A semiconductor device (300), comprising a plurality of transistor cells (3001, 3002), each transistor cell comprising

a trench (314) extending into a drift zone (310) of a semiconductor body (302) from a first surface (304), the drift zone (310) being of a first conductivity type;

a gate electrode structure (324);

a field electrode structure (322) and a first dielectric structure (326) in the trench (314); and

wherein

the first dielectric structure (326) in the trench includes a first part (328) between each one of opposite sidewalls of the trench (314) and the field electrode structure (322), a second part (330) between a bottom side of the trench (314) and the field electrode structure (322), and a third part (332) between each one of opposite sidewalls of the trench (314) and the gate electrode structure (324), the first part (328) having a first thickness d₁ in a direction parallel to the first surface (304), the second part (330) having a second thickness d₂ in a direction perpendicular to the first surface (304), the third part (332) having a third thickness d₃ in a direction parallel to the first surface (304), the first thickness being smaller than the second thickness, and the third thickness being smaller than the first thickness.

17. The semiconductor device of claim 16, wherein the second part (330) of the first dielectric structure (326) includes a stack of electrically insulating materials.

18. The semiconductor device of claim 16, wherein d₂>

2×

d₁.

21. A method for forming a semiconductor device comprising a plurality of transistor cells, wherein forming each transistor cell comprises:

forming a trench extending into a drift zone of a semiconductor body from a first surface, the drift zone being of a first conductivity type;

forming a doped region surrounded by the drift zone and lining a bottom side of the trench, the doped region being of a first conductivity type having a doping concentration lower than the drift zone,

forming a first dielectric structure and a field electrode structure in the trench; and

forming a gate electrode structure, wherein the first dielectric structure includes a field dielectric part between each one of opposite sidewalls of the trench and the field electrode structure, and a gate dielectric part between each one of opposite sidewalls of the trench and the gate electrode structure, wherein a thickness of the gate dielectric part is smaller than a thickness of the field dielectric part.

22. The method of claim 21, wherein forming the doped region comprises introducing dopants through the trench into the drift zone after forming the first dielectric structure.

23. The method of claim 21, wherein forming the first dielectric structure comprises a first part at sidewalls of the trench, and a second part at a bottom side of the trench, the first part having a first thickness d₁ in a direction parallel to the first surface and the second part having a second thickness d₂ in a direction perpendicular to the first surface, the first thickness being smaller than the second thickness.

24. The method of claim 23, wherein forming the first dielectric structure includes high density plasma processing.