PHASE-LOCKED LOOP CIRCUIT WITH IMPROVED PERFORMANCE

• US 20160020773A1
• Filed: 07/16/2014
• Published: 01/21/2016
• Est. Priority Date: 07/16/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Via Telecom Co., Ltd.
• Inventors: YU, Shih-An, LIU, Sen-You, LIAO, Fang-Ren, SU, Yi-Pei
• Granted Patent: US 9,294,104 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03C 3/0933 using fractional frequency division in the feedback loop of the phase locked loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0893 the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/1972 for reducing the locking time interval H03L7/1974, H03L7/199 take precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

Claims

1. A phase-locked loop circuit, comprising:

a first phase detector receiving a first reference signal with a first reference frequency and a first feedback signal with a first feedback frequency to generate a first up/down signal;

a first charge pump comprising a positive output node and a negative output node, wherein the first charge pump receives the first up/down signal to generate a first current signal;

a capacitor, coupled between the negative output node of the first charge pump and the ground; and

a capacitor multiplier, coupled to the negative output node of the first charge pump, receiving the first reference signal and the first feedback signal to generate a second current signal, wherein the second current signal is the first current signal divided by a first scaling number.

2. The phase-locked loop circuit of claim 1, wherein the capacitor multiplier comprises:

a first frequency divider, comprising the first scaling number, receiving the first reference signal to generate a second reference signal with a second reference frequency, wherein the second reference frequency is the first reference frequency divided by the first scaling number; and

a second frequency divider, comprising the first scaling number, receiving the first feedback signal to generate a second feedback signal with a second feedback frequency, wherein the second feedback frequency is the first feedback frequency divided by the first scaling number.

3. The phase-locked loop circuit of claim 1, further comprising:

a filter, coupled between the positive output node and the negative output node, receiving the first current signal to generate a control signal;

a voltage-controlled oscillator, generating an output signal with an output frequency by using the control signal; and

a third frequency divider, comprising a second scaling number, generating the first feedback signal with the first feedback frequency, wherein the first feedback frequency is the output frequency divided by the second scaling number.

4. The phase-locked loop circuit of claim 2, wherein the capacitor multiplier further comprises:

a second phase detector receiving the second reference signal and a second feedback signal to generate a second up/down signal; and

a second charge pump coupled to the negative output node, wherein the second charge pump receives the second up/down signal to generate a second current signal.

5. The phase-locked loop circuit of claim 1, wherein the filter comprises:

a resistor coupled between the positive output node and the negative output node, wherein the resistor converts the first current signal to the control signal.

6. The phase-locked loop circuit of claim 1, further comprising:

a crystal oscillator generating a crystal signal with a crystal frequency;

a simplified phase-locked loop circuit receiving the first signal to generate an intermediate signal with an intermediate frequency; and

a fourth frequency divider, comprising a reference scaling number, receiving the intermediate signal to generate the first reference signal.

7. The phase-locked loop circuit of claim 6, wherein the crystal frequency is 19.2 MHz, the intermediate frequency is 26 MHz, the reference scaling number is 4, and the first reference frequency is 104 MHz.

8. The phase-locked loop circuit of claim 1, further comprising:

a modulator, coupled to the first frequency divider, configured to modulate the second scaling number;

a pre-filter comprising a matching transfer function, wherein the matching transfer function is configured to compensate a transfer function of the phase-locked loop circuit; and

a processor receiving the second reference signal and coupled to the pre-filter, wherein the processor generates a modulation signal for modulating the second scaling number.

9. The phase-locked loop circuit of claim 8, wherein the modulator is a second-order delta-sigma modulator, and the second reference frequency is 26 MHz.

10. The phase-locked loop circuit of claim 1, further comprising:

a fifth frequency divider receiving the output signal to generate a system signal with a system frequency, wherein the system frequency is the output frequency divided by an output scaling number, and wherein the output scaling number is 4.

11. The phase-locked loop circuit of claim 2, wherein the first scaling number is 4, and the second reference frequency is 26 MHz.

12. A phase-locked loop circuit, comprising:

a first phase detector receiving a first reference signal with a first reference frequency and a first feedback signal with a first feedback frequency to generate a first up/down signal;

a first charge pump comprising a first output node, wherein the first charge pump receives the first up/down signal to generate a first current signal at the first output node;

a capacitor, coupled to a second output node; and

a capacitor multiplier, comprising the second output node, receiving the first reference signal and the first feedback signal to generate a second current signal on the second output node, wherein the second current signal is reversed phase to the first current signal.

13. The phase-locked loop circuit of claim 12, wherein the capacitor multiplier comprises:

a first frequency divider, comprising a first scaling number, receiving the first reference signal to generate a second reference signal with a second reference frequency, wherein the second reference frequency is the first reference frequency divided by the first scaling number; and

a second frequency divider, comprising the first scaling number, receiving the first feedback signal to generate a second feedback signal with a second feedback frequency, wherein the second feedback frequency is the first feedback frequency divided by the first scaling number.

14. The phase-locked loop circuit of claim 12, further comprising:

a filter, coupled to the first output node and the second output node, receiving the first current signal to generate a control signal;

a voltage-controlled oscillator, generating an output signal with an output frequency by using the control signal; and

a third frequency divider, comprising a second scaling number, generating the first feedback signal with the first feedback frequency, wherein the first feedback frequency is the output frequency divided by the second scaling number.

15. The phase-locked loop circuit of claim 14, wherein the capacitor multiplier further comprises:

a second phase detector receiving a second reference signal and a second feedback signal to generate a second up/down signal; and

a second charge pump coupled to the second output node, wherein the second charge pump receives the second up/down signal to generate a second current signal.

16. The phase-locked loop circuit of claim 12, wherein the filter comprises:

a resistor coupled between the first output node and the second output node, wherein the resistor converts the first current signal to the control signal.

17. The phase-locked loop circuit of claim 12, further comprising:

a crystal oscillator generating a crystal signal with a crystal frequency;

a simplified phase-locked loop circuit receiving the first signal to generate an intermediate signal with an intermediate frequency; and

a fourth frequency divider, comprising a reference scaling number, receiving the intermediate signal to generate the first reference signal.

18. The phase-locked loop circuit of claim 17, wherein the crystal frequency is 19.2 MHz, the intermediate frequency is 26 MHz, the reference scaling number is 4, and the first reference frequency is 104 MHz.

19. The phase-locked loop circuit of claim 15, further comprising:

a modulator, coupled to the first frequency divider, configured to modulate the second scaling number;

a pre-filter comprising a matching transfer function, wherein the matching transfer function is configured to compensate a transfer function of the phase-locked loop circuit; and

a processor receiving the second reference signal and coupled to the pre-filter, wherein the processor generates a modulation signal for modulating the second scaling number.

20. The phase-locked loop circuit of claim 19, wherein the modulator is a second-order delta-sigma modulator, and the second reference frequency is 26 MHz.

21. The phase-locked loop circuit of claim 12, further comprising:

a fifth frequency divider receiving the output signal to generate a system signal with a system frequency, wherein the system frequency is the output frequency divided by an output scaling number, and wherein the output scaling number is 4.

22. The phase-locked loop circuit of claim 13, wherein the first scaling number is 4, and the second reference frequency is 26 MHz.