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PHASE-LOCKED LOOP (PLL)

  • US 20160020775A1
  • Filed: 07/16/2014
  • Published: 01/21/2016
  • Est. Priority Date: 07/16/2014
  • Status: Active Grant
First Claim
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1. A phase-locked loop (PLL), comprising:

  • a clock adjuster configured to;

    receive an initial clock signal having an initial frequency;

    receive a mode control signal; and

    responsive to a change in a phase error signal of the PLL being below an error threshold, modify the initial clock signal to a first clock signal based on the mode control signal, the first clock signal having a first frequency; and

    a loop filter configured to generate a loop filter output signal based on the first clock signal, the loop filter output signal controlling a bandwidth of the PLL.

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