CIRCUIT SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

• US 20160021753A1
• Filed: 07/17/2015
• Published: 01/21/2016
• Est. Priority Date: 07/17/2014
• Status: Active Grant

• Current Assignee: Ibiden Co., Ltd.
• Original Assignee: Ibiden Co., Ltd.
• Inventors: TOMIKAWA, Mitsuhiro, ASANO, Koji
• Granted Patent: US 9,955,591 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0206 by printed thermal vias
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/185 Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/10 Details of components or other objects attached to or integrated in a printed circuit board
• CPC Class Codes: H05K 2201/10045 Mounted network component having plural terminals
• CPC Class Codes: H05K 2201/10416 : Metallic blocks or heatsinks completely inserted in a PCB metallic supports H05K3/0061
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4697 : having cavities, e.g. for mounting components H05K3/4691 takes precedence

Abstract

A circuit substrate includes a core substrate having a cavity penetrating through the substrate, a combined component accommodated in the cavity of the substrate, a first build-up layer laminated on first surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, a second build-up layer laminated on second surface of the substrate and including an insulating layer such that the insulating layer is covering the cavity, and a filling resin filling gap formed between the cavity and combined component accommodated in the cavity of the substrate. The combined component includes an electronic component and a metal block, the electronic component has terminal surface on side facing the first surface of the substrate, and the metal block is superposed to surface of the electronic component on the opposite side of the electronic component with respect to the terminal surface.

Claims

1. A circuit substrate, comprising:

a core substrate having a cavity penetrating through the core substrate;

a combined component accommodated in the cavity of the core substrate;

a first build-up layer laminated on a first surface of the core substrate and comprising an insulating resin layer such that the insulating resin layer is covering the cavity;

a second build-up layer laminated on a second surface of the core substrate and comprising an insulating resin layer such that the insulating resin layer is covering the cavity; and

a filling resin filling a gap formed between the cavity and the combined component accommodated in the cavity of the core substrate,

wherein the combined component comprises an electronic component and a metal block, the electronic component has a terminal surface on a side facing the first surface of the core substrate, and the metal block is superposed to a surface of the electronic component on an opposite side of the electronic component with respect to the terminal surface.

2. A circuit substrate according to claim 1, wherein the first build-up layer comprises a plurality of via conductors connected to a plurality of terminal pads of the electronic component in the combined component, respectively, and the first build-up layer comprises a plurality of via conductors connected to the metal block of the combined component.

3. A circuit substrate according to claim 1, wherein the core substrate comprises a first conductor circuit layer forming the first surface of the core substrate and a second conductor circuit layer forming the second surface of the core substrate, and the combined component is accommodated in the cavity of the core substrate such that the terminal surface of the electronic component is positioned at an interface between the first build-up layer and the first conductor circuit layer and the metal block has a surface positioned at an interface between the second build-up layer and the second conductor circuit layer.

4. A circuit substrate according to claim 3, wherein the metal block has a thickness which is greater than a thickness of each of the first and second conductor circuit layers.

5. A circuit substrate according to claim 1, wherein the metal block has a surface facing the electronic component and having a width which is greater than a width of a surface of the electronic component facing the metal block.

6. A circuit substrate according to claim 1, wherein the combined component comprises a conductive adhesive layer formed between the metal block and the electronic component such that the conductive adhesive layer is adhering the metal block and the electronic component.

7. A circuit substrate according to claim 1, wherein the metal block has a roughened surface having an arithmetic average roughness in a range of 0.1 to 3.0 such that the roughened surface is in contact with the insulating resin layer of the second build-up layer.

8. A circuit substrate according to claim 1, wherein the first build-up layer has an electronic component mounting structure positioned directly above the combined compound and configured to mount a second electronic component on an outer surface of the first build-up layer, and a substrate mounting structure positioned to surround the electronic component mounting structure and configured to mount a second circuit substrate on the outer surface of the first build-up layer.

9. A circuit substrate according to claim 1, wherein the metal block is connected to a grounding circuit formed in the second build-up layer.

10. A circuit substrate according to claim 2, wherein the core substrate comprises a first conductor circuit layer forming the first surface of the core substrate and a second conductor circuit layer forming the second surface of the core substrate, and the combined component is accommodated in the cavity of the core substrate such that the terminal surface of the electronic component is positioned at an interface between the first build-up layer and the first conductor circuit layer and the metal block has a surface positioned at an interface between the second build-up layer and the second conductor circuit layer.

11. A circuit substrate according to claim 10, wherein the metal block has a thickness which is greater than a thickness of each of the first and second conductor circuit layers.

12. A circuit substrate according to claim 2, wherein the metal block has a surface facing the electronic component and having a width which is greater than a width of a surface of the electronic component facing the metal block.

13. A circuit substrate according to claim 2, wherein the combined component comprises a conductive adhesive layer formed between the metal block and the electronic component such that the conductive adhesive layer is adhering the metal block and the electronic component.

14. A circuit substrate according to claim 2, wherein the metal block has a roughened surface having an arithmetic average roughness in a range of 0.1 to 3.0 such that the roughened surface is in contact with the insulating resin layer of the second build-up layer.

15. A circuit substrate according to claim 2, wherein the first build-up layer has an electronic component mounting structure positioned directly above the combined compound and configured to mount a second electronic component on an outer surface of the first build-up layer, and a substrate mounting structure positioned to surround the electronic component mounting structure and configured to mount a second circuit substrate on the outer surface of the first build-up layer.

16. A circuit substrate according to claim 2, wherein the metal block is connected to a grounding circuit formed in the second build-up layer.

17. A method for manufacturing a circuit substrate, comprising:

forming a cavity penetrating through a core substrate;

proving a combined component comprising an electronic component and a metal block in the cavity of the core substrate;

filling a filling resin into a gap formed between the cavity and the combined component accommodated in the cavity of the core substrate;

forming a first build-up layer comprising an insulating resin layer on a first surface of the core substrate such that the insulating resin layer covers the cavity; and

forming a second build-up layer comprising an insulating resin layer on a second surface of the core substrate such that the insulating resin layer covers the cavity.

18. A method for manufacturing a circuit substrate according to claim 17, further comprising:

adhering the metal block and the electronic component such that the combined component is formed,

wherein the providing of the combined component comprises accommodating the accommodating of the combined component comprising the electronic component and the metal block into the cavity.

19. A method for manufacturing a circuit substrate according to claim 17, wherein the providing of the combined component comprises positioning the metal block in the cavity and adhering the combined component onto the metal block in the cavity.

20. A method for manufacturing a circuit substrate according to claim 17, wherein the providing of the combined component comprises positioning the metal block in the cavity and adhering the combined component onto the metal block in the cavity such that the electronic component has a terminal surface on a side facing the first surface of the core substrate and the metal block is superposed to a surface of the electronic component on an opposite side of the electronic component with respect to the terminal surface.