SEMICONDUCTOR MEMORY APPARATUS AND ELECTRONIC SYSTEM HAVING THE SAME

• US 20160026396A1
• Filed: 10/01/2014
• Published: 01/28/2016
• Est. Priority Date: 07/24/2014
• Status: Abandoned Application

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: PARK, Hae Chan
• Application Number:
  US14/504,228
• Publication Number:
  US 20160026396A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: H04B 7/24 for communication between two or more posts wireless communication networks H04W

Abstract

A semiconductor memory apparatus includes a memory circuit unit, a radio frequency (RF) signal unit which wirelessly transmits and receives signals, and a control circuit unit which accesses the memory circuit unit in response to a signal received through the RF signal unit and provides data of the memory circuit unit to the RF signal unit. At least one of the RF signal unit and the control circuit unit has a one-chip structure with the memory circuit unit.

Claims

1. A semiconductor memory apparatus comprising;

a memory circuit unit;

a radio frequency (RF) sign unit suitable to wirelessly transmit and receive a first signal; and

a control circuit unit suitable to access the memory circuit unit in response to a second signal received through the RF signal unit and further suitable to provide data of the memory circuit unit to the RF signal unit,

wherein at least one of the RF signal unit and the control circuit unit is provided in a single chip together with the memory circuit unit.

2. The semiconductor memory apparatus of claim 1, wherein the memory circuit unit and the RF signal unit are formed in a first chip, and

wherein the control circuit unit is formed in a second chip.

3. The semiconductor memory apparatus of claim 1, wherein the memory circuit unit and the control circuit unit are formed in a first chip, and

wherein the RF signal unit is formed in a second chip.

4. The semiconductor memory apparatus of claim 1 wherein the RF signal unit includes:

a transmitting unit suitable to wirelessly transmit a third signal which is provided from the control circuit unit; and

a receiving unit suitable to wirelessly receive a fourth signal from an external apparatus and provide the fourth signal to the control circuit unit.

5. The semiconductor memory apparatus of claim 4, wherein the RF signal unit further includes a voltage generation unit, and

wherein the voltage generation unit is suitable to generate an operation voltage in response to a fifth signal wirelessly provided from the external apparatus.

6. The semiconductor memory apparatus of claim 5, wherein the voltage generation unit includes:

a voltage multiplication unit suitable to generate a direct current (DC) voltage and boost the generated DC voltage in response to a sixth signal wirelessly provided from the external apparatus; and

a charging unit suitable to store the DC voltage boosted in the voltage multiplication unit and provide the DC voltage as an operation voltage.

7. The semiconductor memory apparatus of claim 6, wherein the memory circuit unit and the charging unit are formed in a first chip, and

wherein the control circuit unit, the transmitting unit, the receiving unit, and the voltage multiplication unit are formed in a second chip different from the first chip.

8. The semiconductor memory apparatus of claim 6, wherein the memory circuit unit, the control circuit unit, and the charging unit are formed in a first chip, and

wherein the transmitting unit, the receiving unit, and the voltage multiplication unit are formed in a second chip different from the first chip.

9. The semiconductor memory apparatus of claim 1, wherein the control circuit unit includes:

a signal processor suitable to modulate a seventh signal, which is to be transmitted to an external apparatus, provide the modulated signal to the RF signal unit, and demodulate an eighth signal which is provided from the RF signal unit;

a clock generator suitable to generate a clock signal and provide the clock signal to the RF signal unit; and

a controller suitable to access the memory circuit unit in response to a ninth signal provided from the signal processor.

10. An electronic system comprising:

a first chip including a radio frequency (RF) signal unit; and

at least one second chip suitable to wirelessly transmit a first signal to the first chip and receive a second signal from the first chip,

wherein the second chip includes;

a memory circuit unit;

a radio frequency (RF) signal unit configured to wirelessly transmit a third signal and receive a fourth signal; and

a control circuit unit configured to access the memory circuit unit in response to a fifth signal received through the RF signal unit and provide data of the memory circuit unit to the RF signal unit,

wherein at least one of the RF signal unit and the control circuit unit is provided in a single chip together with the memory circuit unit.

11. The electronic system of claim 10, wherein a plurality of second chips mutually transmit and receive a sixth signal with each other, and with the first chip.

12. The electronic system of claim 10 wherein the first chip is a host apparatus.

13. The electronic system of claim 10, wherein the RF signal unit includes:

a transmitting unit suitable to wirelessly send a seventh signal provided from the control circuit unit; and

a receiving unit suitable to wirelessly receive an eighth signal from an external apparatus and provide the eighth signal to the control circuit unit.

14. The electronic system of claim 13, wherein the RF signal unit further includes a voltage generation unit, and

wherein the voltage generation unit is suitable to generate an operation voltage in response to a ninth signal wirelessly provided from the external apparatus.

15. The electronic system of claim 14, wherein the voltage generation unit includes:

a voltage multiplication unit suitable to generate a direct current (DC) voltage and boost the generated DC voltage in response to a tenth signal wirelessly provided from the external apparatus; and

a charging unit suitable to store the DC voltage boosted in the voltage multiplication unit and provide the stored DC voltage as the operation voltage.

16. The electronic system of claim 10, wherein the control circuit unit includes:

a signal processor suitable to modulate an eleventh signal, which is to be transmitted to an external apparatus, provide the modulated signal to the RF signal unit, and demodulate a twelfth signal provided from the RF signal unit;

a clock generator suitable to generate a clock signal and provide the clock signal to the RF signal unit; and

a controller suitable to access the memory circuit unit in response to a thirteenth signal provided from the signal processor.

17. An electronic system comprising:

a processor suitable to decode a command input provided from an external apparatus;

a memory controller suitable to wirelessly transmit and receive a first signal to and from a memory apparatus according to control of the processor; and

a memory apparatus, wherein the memory apparatus includes;

a memory circuit unit,

a radio frequency (RF) signal unit suitable to wirelessly transmit and receive a second signal to and from the memory controller, and

a control circuit unit suitable to access the memory circuit unit in response to a third signal received through the RF signal unit and provide data of the memory circuit unit to the RF signal unit,

wherein at least one of the RF signal unit and the control circuit unit is provided in a single chip together with the memory circuit unit.

18. An electronic system comprising:

a memory apparatus, wherein the memory apparatus includes;

a memory circuit unit,

a radio frequency (RF) signal unit suitable to wirelessly transmit and receive a first signal, and

a control circuit unit suitable to access the memory circuit unit in response to a second signal received through the RF signal unit and provide data of the memory circuit unit to the RF signal unit,

wherein at least one of the RF signal unit and the control circuit unit is provided on a single chip together with the memory circuit unit;

a memory controller suitable to wirelessly transmit and receive a third signal to and from the control circuit unit, and control operation of the memory apparatus; and

a card interface suitable to perform a data exchange between a host and the memory controller.