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SM4 ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS

  • US 20160026468A1
  • Filed: 07/22/2014
  • Published: 01/28/2016
  • Est. Priority Date: 07/22/2014
  • Status: Active Grant
First Claim
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1. A processor comprising:

  • a plurality of packed data registers;

    a decode unit to decode an instruction, the instruction to indicate one or more source packed data operands, the one or more source packed data operands to have four 32-bit results of four prior SM4 cryptographic rounds, and four 32-bit values; and

    an execution unit coupled with the decode unit and the plurality of the packed data registers, the execution unit, in response to the instruction, to store four 32-bit results of four immediately subsequent and sequential SM4 cryptographic rounds in a destination storage location that is to be indicated by the instruction.

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