POWER AWARE TASK SCHEDULING ON MULTI-PROCESSOR SYSTEMS

• US 20160026507A1
• Filed: 07/24/2015
• Published: 01/28/2016
• Est. Priority Date: 07/24/2014
• Status: Active Grant

• Current Assignee: Qualcomm Innovation Center Incorporated (Qualcomm, Inc.)
• Original Assignee: Qualcomm Innovation Center Incorporated (Qualcomm, Inc.)
• Inventors: Vaddagiri, Srivatsa, Muckle, Stephen, Mustafa, Syed Rameez
• Granted Patent: US 9,785,481 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Methods and apparatus for power-based scheduling of tasks among processors are disclosed. A method may include executing processor executable code on one or more of the processors to prompt a plurality of executable tasks for scheduling among the processors. Processor-demand information is obtained about the plurality of executable tasks in addition to capacity information for each of the processors. Processor power information for each of the processors is also obtained, and the plurality of executable tasks are scheduled on the lowest power processors where processor-demands of the tasks are satisfied.

Claims

1. A computing device, the computing device comprising:

N processors, N greater than one, wherein at least two of the N processors differ with respect to a level of power that each of the at least two processors draws, wherein N is greater than one;

a power-based scheduler configured to;

obtain information about processor-demand for each of a plurality of tasks;

obtain capacity information for each of the N processors;

obtain processor-power information for each of the N processors; and

schedule each of the plurality of tasks among the N processors based upon the information about processor-demand, the capacity information, and the processor-power information to reduce overall power consumption of the N processors.

2. The computing device of claim 1, wherein the processor-power information for each of the N processors includes a power value for each of a plurality of frequencies.

3. The computing device of claim 1, wherein the power-based scheduler includes:

a task characterization module configured, upon wakeup of a particular task, to characterize the particular task as either a small task or a non-small task;

a processor characterization module configured to distinguish each of the N processors based on whether each of the N processors surpasses a per-processor idle threshold;

a power-based task wakeup module configured to schedule the particular task to one of the N processors based upon whether the particular task is a small task or a non-small task, the processor-power information for each of the N processors, whether the task fits on each of the N processors, and whether each of the N processors passes the per-processor idle threshold.

4. The computing device of claim 3, wherein the power-based task wakeup module, for non-small tasks, is configured to schedule the particular task to one of the N processors based upon the processor power cost.

5. The computing device of claim 1, wherein the power-based scheduler includes:

a power-based load balancer configured to distribute tasks among the N processors in a nonrandom fashion based on each processor'"'"'s power efficiency and load, to improve total power efficiency and reduce total load imbalance among the N processors.

6. The computing device of claim 1, wherein the power-based scheduler includes:

a power-based scheduler tick configured to check on processor-bound tasks at a periodic interval and redistribute the processor-bound tasks based on processor power efficiency and processor idleness to improve total power efficiency among the N processors over the course of the runtime of tasks.

7. A method for scheduling processor executable tasks among N processors of a computing device, the method comprising:

executing processor executable code on one or more of the N processors to prompt scheduling of a plurality of executable tasks among the N processors;

obtaining processor-demand information about the plurality of executable tasks;

obtaining capacity information for each of the N processors;

obtaining processor power information for each of the N processors; and

scheduling each of the plurality of tasks among the N processors based upon the information about processor-demand, the capacity information, and the processor-power information to reduce overall power consumption of the N processors.

8. The method of claim 7, wherein the scheduling of the plurality of executable tasks includes:

characterizing, upon wakeup, each task as either a small task or a non-small task;

distinguishing each of the N processors based on whether each one exceeds a per-processor idle threshold;

scheduling a particular task to one of the N processors based upon whether the particular task is a small task or a non-small task, the power information of each of the N processors, whether the task fits on each of the N processors, and whether each of the N processors surpasses the per-processor idle threshold.

9. The method of claim 8, wherein the scheduling of the particular task, for non-small tasks, includes:

determining which of the N processors the non-small task fits on;

determining which of the N processors surpass the per-processor idle threshold;

determining which of the N processors is in a lowest power band;

determining which of the N processors is least loaded;

determining which of the N processors is lowest cost; and

scheduling the particular non-small task to one of the N processors based on the determinations.

10. The method in claim 8, wherein the scheduling of the particular task, for small tasks, includes:

determining which of the N processors is in a lowest power band;

determining which of the N processors surpass the per-processor idle threshold;

determining which of the N processors is least loaded;

determining a c-state of each of the N processors; and

scheduling the particular small task to one of the N processors based on the determinations.

11. The method of claim 7, including:

distributing tasks among the N processors in a nonrandom fashion based on each individual processor'"'"'s power efficiency and load to improve total power efficiency and reduce total load imbalance among the N processors.

12. The method of claim 7, including:

checking on processor-bound tasks at a periodic interval and redistributing the processor-bound tasks based on processor power efficiency and processor idleness to improve total power efficiency among the N processors over a course of the runtime of tasks.

13. A non-transitory, tangible processor readable storage medium, encoded with processor readable instructions to perform a method for operating a plurality of processors on a communication device, the method comprising:

scheduling processor executable tasks among N processors of a computing device, the method comprising;

executing processor executable code on one or more of the N processors to prompt scheduling of a plurality of executable tasks among the N processors;

obtaining processor-demand information about the plurality of executable tasks;

obtaining capacity information for each of the N processors;

obtaining processor power information for each of the N processors; and

scheduling each of the plurality of tasks among the N processors based upon the information about processor-demand, the capacity information, and the processor-power information to reduce overall power consumption of the N processors.

14. The non-transitory, tangible processor readable storage medium of claim 13, wherein the scheduling of the plurality of executable tasks includes:

characterizing, upon wakeup, each task as either a small task or a non-small task;

distinguishing each of the N processors based on whether each one exceeds a per-processor idle threshold;

scheduling a particular task to one of the N processors based upon whether the particular task is a small task or a non-small task, the power information of each of the N processors, whether the task fits on each of the N processors, and whether each of the N processors surpasses the per-processor idle threshold.

15. The non-transitory, tangible processor readable storage medium of claim 14, wherein the scheduling of the particular task, for non-small tasks, includes:

determining which of the N processors the non-small task fits on;

determining which of the N processors surpass the per-processor idle threshold;

determining which of the N processors is in a lowest power band;

determining which of the N processors is least loaded;

determining which of the N processors is lowest cost; and

scheduling the particular non-small task to one of the N processors based on the determinations.

16. The non-transitory, tangible processor readable storage medium in claim 14, wherein the scheduling of the particular task, for small tasks, includes:

determining which of the N processors is in a lowest power band;

determining which of the N processors surpass the per-processor idle threshold;

determining which of the N processors is least loaded;

determining a c-state of each of the N processors; and

scheduling the particular small task to one of the N processors based on the determinations.

17. The non-transitory, tangible processor readable storage medium of claim 13, the method including:

distributing tasks among the N processors in a nonrandom fashion based on each individual processor'"'"'s power efficiency and load to improve total power efficiency and reduce total load imbalance among the N processors.

18. The non-transitory, tangible processor readable storage medium of claim 13, the method including:

checking on processor-bound tasks at a periodic interval and redistributing the processor-bound tasks based on processor power efficiency and processor idleness to improve total power efficiency among the N processors over a course of the runtime of tasks.